{"title":"国際会議：AVIC","description":"\u003cp style=\"padding-left: 40px;\"\u003e＜他の国際会議＞\u003c\/p\u003e\n\u003cul\u003e\n\u003cli style=\"list-style-type: none;\"\u003e\n\u003cul\u003e\n\u003cli\u003e\n\u003ca href=\"https:\/\/ieej.bookpark.ne.jp\/collections\/kk-2010korea\"\u003e2010 Korea - Japan Joint Technical Workshop on Semiconductor Power Converter\u003c\/a\u003e\u003ca href=\"https:\/\/ieej.bookpark.ne.jp\/collections\/kk-2010korea\"\u003e\u003c\/a\u003e\n\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"https:\/\/ieej.bookpark.ne.jp\/collections\/kk-samcon\"\u003eSAMCON\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"https:\/\/ieej.bookpark.ne.jp\/collections\/kk-acis\"\u003eACIS\u003c\/a\u003e\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e","products":[{"product_id":"ieej-avic2025a1","title":"Low-power SEAL-RF adiabatic logic circuit with DC bias power supply","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eA1\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eMarina Shibata (Gifu University), Yasuhiro Takahashi (Gifu University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eAdiabatic Logic Circuit,Energy Efficient Devices,Low power dissipation,DC power supply\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eIn this work, we propose a circuit configuration that incorporates a DC bias power supply into a SEAL-RF adiabatic logic circuit. The proposed circuit prevents complete discharge of the output node by maintaining it at a voltage of 0.2 V–0.3 V, thereby suppressing energy loss during discharge. In addition, the remaining charge at the output node contributes to reducing the energy required for recharging in the next clock cycle. As a result, the proposed circuit demonstrates superior power efficiency compared with conventional configurations, especially, it is effective in AND\/NAND, XOR\/XNOR, and BUFF\/INV configurations. Simulation results show that a 65.6% reduction in energy consumption was achieved compared to a conventional SEAL-RF circuit when 100 logic circuits are connected in an AND\/NAND configuration.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e1-4p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e481Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656263516399,"sku":"IEEJ-AVIC2025A1-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_2750396f-c595-48f2-92d4-5014b9865d83.png?v=1770624974"},{"product_id":"ieej-avic2025a2","title":"The SSHC compaction method using capacitor reusing technique","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eA2\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eYusuke Kakinuma (Tokyo University of Science), Ryoichi Miyauchi (Tokyo University of Science), Akira Hyogo (Tokyo University of Science)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003ePiezoelectric energy harvesting,rectifier,Synchronized Switch Harvesting on Capacitors (SSHC)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper presents a capacitor reusing technique for Synchronous Switch Harvesting on Capacitor (SSHC) circuits in piezoelectric energy harvesters (PEH). PEH is a technology that converts mechanical vibration energy into electrical energy using piezoelectric transducers. However, such devices suffer from power loss caused by parasitic capacitance. SSHC is one of the techniques developed to reduce this loss, based on switchedcapacitor circuits. To achieve effective charge inversion, however, it often requires either large capacitance values or multiple SSHC stages. In the proposed circuit, the switch configuration of SSHC is modified to allow capacitors to be connected in series. This enables capacitor reuse, making it possible to achieve 2^(n-1) stages of operation using only n capacitors. Simulation results confirmed that the voltage flipping efficiency (VFE) improved by up to 12.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e5-8p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e820Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656264073455,"sku":"IEEJ-AVIC2025A2-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_c21d1651-7b3e-4868-852a-1d066e999b29.png?v=1770624980"},{"product_id":"ieej-avic2025a3","title":"A design of a new lossy FDNR employing VCII","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eA3\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eDaichi Shigihara (National Defence Academy), Fujihiko Matsumoto (National Defence Academy), Kazuki Hatai (National Defence Academy)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eAnalog Integrated Circuits,Active Filters,VCII,Bruton Transformation, FDNR\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eIn this paper, the authors propose a method to realize a new lossy FDNR. From the equivalent circuit of the conventional lossy FDNR, the proposed lossy FDNR designed with VCII is derived. Simulations and experiments are performed proposed lossy FDNR to confirm the characteristics and operation. As a result, effectiveness of the proposed FDNR is verified.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e9-12p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e2,892Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656264466671,"sku":"IEEJ-AVIC2025A3-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_4a1393d3-d24e-499e-a6dd-80f1b9029946.png?v=1770624985"},{"product_id":"ieej-avic2025a4","title":"A method to construct FDNR without requiring capacitance matching and its application to lowfrequency LPF","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eA4\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eTsuyoshi Ito (National Defence Academy), Takashi Nishi (National Defence Academy), Fujihiko Matsumoto (National Defence Academy)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eAnalog Integrated Circuits,Low Frequency LPF,Active Filters,the Bruton Transformation,FDNR,CCII\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eLow-frequency Low-pass filters (LPF) are used in biomedical signal processing devices. LPFs are basically designed using inductors and capacitors. The Bruton transformation is a concept that enables integration of filters without the use of inductors. Capacitors are transformed to FDNRs (Frequency-Dependent Negative Resistance) by the Bruton transformation. Although the conventional FDNR can be realized using two CCII （second generation Current Conveyor), process variations in the integrated capacitors lead to deviation from the ideal characteristics. This paper proposes a method to realize an FDNR which does not require capacitance matching. In addition, the proposed circuit can reduce the capacitance using capacitance scaling techniques.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e13-16p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e1,104Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656264859887,"sku":"IEEJ-AVIC2025A4-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_74476f96-a2f9-449c-8236-4b2284351192.png?v=1770624990"},{"product_id":"ieej-avic2025a5","title":"Analog LSI design platform for open source silicon development and porting","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eA5\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eSeijiro Moriyama (Anagix Corporation), Chikau Takahashi (Takamori Co., Ltd.), Kazuhiro Shouno (University of Tsukuba), Hiroshi Tanimoto (Kitami Institute of Technology), Shingo Ura (Logic Research Co., Ltd.), Tadaaki Tsuchiya (Logic Research Co., Ltd.)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eOpen Source,Analog,Design Platform,LSI design democritazation,PDK,PCell,Minimal Fab,Klayout\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eWe advocate a platform for design democratization that allows more people to participate in semiconductor design. We adopt the OpenPDK method, which makes it easier to port design data among different fabs. Since compatible PCells are used at the source and destination fabs, design rules inside the device are preserved. Rule violations between devices may need manual resolution, still porting layout is easier than before. Unlike digital circuits, porting analog circuits requires circuit redesign that cares differences in device characteristics. The main objectives of the design platform are to represent reusable design information, perform parametric analysis to confirm design specifications, compare device characteristics, and convert design data to different formats. We will introduce open source silicon development samples to show how the design platform has been utilized.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e17-20p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e518Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656265220335,"sku":"IEEJ-AVIC2025A5-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_ea01fb44-8294-4665-a96d-1d233c8e0764.png?v=1770624996"},{"product_id":"ieej-avic2025a6","title":"High-speed a four-armed bandit problem solving IC in CMOS 180 nm technology","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eA5\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eTomoki Furuta (Meiji University), Rin Tsuboi (Meiji University), Kawori Sekine (Meiji University), Kazuyuki Wada (Meiji University), Shinsuke Hara (National Institute of Information and Communications Technology), Satoru Tanoi (National Institute of Information and Communications Technology), Akifumi Kasamastu (National Institute of Information and Communications Technology)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eMulti-armed bandit problem,Machine learning,Integrated circuit,CMOS,CML latch\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis study expands a previously developed GHzband two-armed bandit (2AB) problem solving IC into a fourarmed bandit (4AB) problem-compatible circuit, thereby enabling learning from a wider range of options to select the optimal one. In addition to modifying the timing chart and redesigning the component values of the current-mode-logic (CML) latch, we introduced a multiplexer control signal generation circuit and optimized its device parameters to achieve high-speed operation. Simulation results demonstrated that the proposed circuit successfully learns the optimal slot machine at a system clock frequency of 3 GHz, confirming its effectiveness and high-speed performance.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e21-24p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e822Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656266105071,"sku":"IEEJ-AVIC2025A6-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_7258e023-dae5-4be8-8355-7e6704058ff3.png?v=1770625001"},{"product_id":"ieej-avic2025b1","title":"High-efficiency walsh LMS-based digital predistortion RF power amplifiers","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eB1\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eMaxandre Fellmann (Universite de Bordeaux), Francois Rivet (Universite de Bordeaux), Nathalie Deltimple (Universite de Bordeaux), Pierre Ferrer (Universite de Bordeaux), Remi Queheille (Universite de Bordeaux), Herve Lapuyade (Universite de Bordeaux), Yann Deval (Universite de Bordeaux), Eric Kerherve (Universite de Bordeaux)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003ePower Amplifier,DPD,Walsh,LMS\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper presents a digital pre-distortion (DPD) for the linearization of RF Power Amplifiers (PAs). Its objective is to improve its convergence speed and reduce its power consumption. The Walsh transform is used as a computational basis to evaluate a predistorter (PD) model. A block-based Walsh Least Mean Squares (WLMS) method is developed to determine the optimal DPD coefficients. Linearization results are presented through simulations and measurements to validate the process in both narrowband and wideband configurations for FR1 5G NR standards. Comparison with conventional DPD algorithms shows that the WLMS converges 10 times faster and consumes up to 20 times less power while maintaining linearization performance comparable to the best DPDs.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e25-28p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e2,140Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656266694895,"sku":"IEEJ-AVIC2025B1-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_20264144-8e77-41db-b2fb-5e61b887e247.png?v=1770625007"},{"product_id":"ieej-avic2025b2","title":"25-28 GHz push-push VCO with flicker noise suppression circuits","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eB2\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eHiyori Kishimoto (Okayama Prefectural University), Kiyotaka Komoku (Okayama Prefectural University), Jun Furuta (Okayama Prefectural University), Yasunori Suzuki (Okayama Prefectural University), Nobuyuki Itoh (Okayama Prefectural University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003ePush-push VCO,Flicker noise,Parallel resonator\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eIn this paper, we investigated circuits designed to suppress flicker noise and reduce the phase noise of the pushpush VCO. We studied three types of circuits, an NMOS pushpush VCO (Sgnd) and connecting a choke inductor (Schoke) or a parallel resonant circuit (Sres) to the source side of the crosscoupled transistor. It was confirmed that Sres and Schoke achieved significant suppression of flicker noise compared to Sgnd in the simulation. However, in the simulation and measurement results, the output power of Sres and Schoke was lower than that of Sgnd, so the phase noise was comparable, or in some cases, worse for Sgnd.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e29-32p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e918Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656268660975,"sku":"IEEJ-AVIC2025B2-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_74777c55-da22-4c06-aec5-7601eee6b1aa.png?v=1770625012"},{"product_id":"ieej-avic2025b3","title":"A proposed TIA circuit based on INV-TIA and RGC-TIA","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eB3\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eKento Samura (Gifu University), Yasuhuiro Takahashi (Gifu University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eTransimpedance amplifier,Optical communication,TIA\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper proposes a new transimpedance amplifier circuit based on an inverter TIA (INV-TIA) circuit and a regulated cascode TIA (RGC-TIA) circuit. The proposed TIA circuit has higher gain and wider bandwidth operation than conventional TIA circuits. Pre-layout simulation shows that the proposed TIA circuit achieves a transimpedance gain of 65.5 dBOmega and a bandwidth of 21.9 GHz. For a supply voltage of 1.2 V, the power consumption is 7.0 mW, the equivalent input current noise is 14.0 pA\/sqrtHz, and the eye aperture is 81%.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e33-36p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e1,949Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656269381871,"sku":"IEEJ-AVIC2025B3-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_a8bddbb2-acd5-436e-b418-344d83494099.png?v=1770625017"},{"product_id":"ieej-avic2025b4","title":"A high-gain 25-Gb\/s active voltage current feedback transimpedance amplifier in 65-nm CMOS","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eB4\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eYudai Taki (Gifu University), Yasuhuiro Takahashi (Gifu University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eTransimpedance amplifier,Optical communication,TIA,AVCF\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper proposes a 25 Gbps, 0.81 pJ\/bit inverterbased Transimpedance Amplifier (TIA) circuit built upon the active voltage-current feedback TIA (AVCF-TIA) architecture. The analysis software is Virtuoso, and the transistors are 65 nm CMOS. Compared to conventional circuits, the proposed TIA circuit exhibits improved gain performance, which is simplified the post amplifier design and contributes to achieving both operational stability and power efficiency. From post-layout simulations, the proposed TIA circuit is confirmed to deliver a transimpedance gain of 75.7 dBOmega and maintain a bandwidth of 20.8 GHz. The proposed TIA circuit operates at a 1.0 V supply voltage with a power consumption of 20.3 mW (=20.3 mA x 1.0 V). The overall layout, including I\/O and DC pads, measures 670 um x 580 μm (=0.39 mm2). The core proposed TIA circuit occupies also an area of 450 um x 176 um (=0.079 mm2) within this footprint.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e37-40p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e1,761Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656269742319,"sku":"IEEJ-AVIC2025B4-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_2cbc5040-f02c-4059-8143-12164f678292.png?v=1770625023"},{"product_id":"ieej-avic2025b5","title":"An energy-efficient 25-Gb\/s common gate feedforward transimpedance amplifier","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eB5\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eHikaru Matsunami (Gifu University), Yasuhuiro Takahashi (Gifu University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eTransimpedance amplifier,Optical communication,TIA,CGFW,Peaking gain\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper presents a common gate-feedforward (CGFW) circuit-based transimpedance amplifier (TIA) with peaking gain. The proposed TIA core circuit has wider bandwidth characteristics than the conventional CGFW circuits. The number of post-amplifier stages can be reduced to one by increasing the gain of the TIA core circuit, resulting in low-power operation. Fabricated in a 65 nm bulk-CMOS technology, the proposed TIA circuit achieves a transimpedance gain of 72.2 dBOmega and a bandwidth of 20.9 GHz. Operating at a supply voltage of 1.1 V, the circuit consumes 18.7 mW (=17.0 mA x 1.1 V). The result is a data rate of 25 Gbps with an energy efficiency of 0.75 pJ\/bit. The total layout area, including I\/O pads and DC pads, is 670 um x 580 um (=0.39 mm2), while the TIA core circuit occupies 470 um x 210 um (=0.099 mm2).\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e41-44p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e2,688Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656270201071,"sku":"IEEJ-AVIC2025B5-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_809c907c-6e5b-447e-b7a7-23f97e035652.png?v=1770625028"},{"product_id":"ieej-avic2025c1","title":"A 728 mV and 23.4 ppm\/degC voltage reference using parasitic diode biasing for temperature compensation in 28 nm FD-SOI technology","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eC1\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eMaxime Guillot (Universite de Bordeaux), Yann Deval (Universite de Bordeaux), Herve Lapuyade (Universite de Bordeaux), Francois Rivet (Universite de Bordeaux)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eVoltage reference,PTAT,CTAT,Back-Gate biasing,Thermal dependency,FD-SOI,Parasitic diode biasing\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper presents a new voltage reference circuit developed in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The proposed voltage reference uses the combination of PTAT and CTAT voltages, along with the implementation of parasitic diode biasing. This biasing approach modifies the behavior of transistors, reducing their thermal dependency. The resulting circuit delivers an output voltage of 728 mV with a temperature coefficient of 23.4 ppm\/degC across a temperature range of -50 degC to 150 degC and under a 1.8 V supply.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e45-48p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e395Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656270594287,"sku":"IEEJ-AVIC2025C1-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_5bd71aea-e4c0-4673-a9a7-2b26545defbe.png?v=1770625033"},{"product_id":"ieej-avic2025c2","title":"PTAT voltage generater-based voltage reference circuit without external bias voltage","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eC2\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eEmu Murata (Meiji University), Kawori Sekine (Meiji University), Shuya Isawa (Meiji University), Michitaka Yoshino (Meiji University), Kazuyuki Wada (Meiji University), Herve Lapuyade (Universite de Bordeaux), Francois Rivet (Universite de Bordeaux), Yann Deval (Universite de Bordeaux)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eVoltage reference circuit,PTAT voltage generator\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eA PTAT voltage generator employed in conventional voltage reference circuits has required a constant external bias voltage. This brought the circuit to malfunction in low-temperature regions. This paper proposes a voltage reference circuit including a bias circuit which gives the voltage with a negative temperature coefficient in order to give a higher PTAT voltage in low-temperature regions. Simulation results demonstrate that the proposed circuit operates correctly over a wider temperature range from 233 K to 423 K.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e49-52p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e679Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656270954735,"sku":"IEEJ-AVIC2025C2-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_01021e0c-62bf-4282-8780-5f49cf274f69.png?v=1770625039"},{"product_id":"ieej-avic2025c3","title":"Thermal profile on IC employing PTAT voltage generator consisting of two MOSFETs","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eC3\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eKeita Hasegawa (Meiji University), Michitaka Yoshino (Meiji University), Kawori Sekine (Meiji University), Kazuyuki Wada (Meiji University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003ePTAT voltage generator circuit,Vptat,Temperature,Power consumption,Distance\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThe temperature distribution on an integrated circuit (IC) chip was evaluated using a PTAT (Proportional To Absolute Temperature) voltage generation circuit. First, by controlling the ambient temperature and measuring the output voltage (Vptat) of the PTAT circuit, we derived a relationship between temperature and Vptat, successfully detecting the temperature dependence of Vptat. Next, by operating a transistor as a localized heat source, we confirmed that the temperature on the IC chip increased proportionally to the amount of heat generated, and that the response time varied depending on the distance from the heat source. These results demonstrate that the PTAT voltage generation circuit can detect temperature distributions on the IC chip based on heating conditions and spatial relationships.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e53-56p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e655Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656271446255,"sku":"IEEJ-AVIC2025C3-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_ee9d3eee-0154-43ef-ac94-cb01841adcdc.png?v=1770625045"},{"product_id":"ieej-avic2025c4","title":"Design and measurement of voltage reference circuit by an equivalent MOSFET having different temperature coefficient of threshold voltage","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eC4\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eShuya Isawa (Meiji University), Michitaka Yoshino (Meiji University), Kawori Sekine (Meiji University), Kazuyuki Wada (Meiji University), Francois Rivet (Universite de Bordeaux), Herve Lapuyade (Universite de Bordeaux), Yann Deval (Universite de Bordeaux)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eVoltage reference circuit,PTAT,Level shift\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper investigates a voltage reference circuit that incorporates an equivalent MOSFET, which adjusts the hreshold voltage and its temperature coefficient using a Proportional To Absolute Temperature (PTAT) voltage generation circuit by measurement. The circuit was designed, fabricated, and measured using the TSMC 180 nm CMOS process. The temperature coefficient of the reference voltage Vref achieved was 480 ppm\/K, and it was confirmed that the circuit operates in the temperature range of 290 K to 370 K.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e57-60p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e784Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656271872239,"sku":"IEEJ-AVIC2025C4-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_babd4e9c-0bed-4135-a234-4e1838e5be90.png?v=1770625051"},{"product_id":"ieej-avic2025c5","title":"Applying gate–source voltage enhancement and threshold voltage reduction techniques to ultralow voltage charge-pump circuit","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eC5\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eArisa Shimizu (Tokyo University of Science), Ryoichi Miyauchi (Tokyo University of Science), Akira Hyogo (Tokyo University of Science)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eRF energy harvesting,Charge pump,Start-up response time,Extremely low voltage input,Body bias effect\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper describes the improvement of the startup response time in an ultra-low voltage input charge-pump boost converter. In RF Energy Harvesting (RFEH), the harvested voltage becomes significantly low when the RF source is far from the receiver or when losses in the rectifier are substantial. Therefore, a charge-pump boost converter is essential to generate a sufficient voltage to operate the subsequent system. Although previous works have proposed individual circuits that apply either gate–source voltage enhancement or threshold voltage reduction, no prior study has combined both techniques in a single design. When combining these techniques, the internal node voltages in the circuit differ significantly from those in conventional designs, requiring careful investigation of optimal connection points. This paper proposes a novel circuit that integrates both techniques to achieve improved performance under ultra-low voltage conditions. Simulation results confirm that the proposed circuit achieves an improvement in start-up response time.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e61-64p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e915Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656272232687,"sku":"IEEJ-AVIC2025C5-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_63e49e75-d204-4426-9cde-907a8e50fbfa.png?v=1770625056"},{"product_id":"ieej-avic2025c6","title":"Active CMOS rectifier circuits with wide input voltage range","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eC6\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eNicodimus Retdian (Shibaura Institute of Technology)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eBand-gap reference,Near field communication,Start up circuit,Temperature compensation\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eActive rectifier is one of important and indispensable analog circuit for wireless power transfer in applications such as RFID and Near Field Communication (NFC). Active rectifier topology such as cross-coupled and self biased CMOS active rectifiers have been proposed. However, these rectifier topologies only offer good power efficiency at a relatively limited range of input voltage. This paper proposes a new topology of CMOS active rectifier which provides a high power efficiency across a wider range of input voltage compared to conventional topologies. The proposed circuit is designed using high voltage device of 0.18 um CMOS process. Measurement results show an average output voltage and ripple of 1.6 V and 0.0 V respectively for input voltage amplitude of 3V and load resistance of 10 kohm. The frequency of input voltage is 13.56 MHz assuming the carrier frequency of NFC system.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e65-68p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e286Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656272593135,"sku":"IEEJ-AVIC2025C6-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_cd9a6c65-1a35-45e2-93cf-3dc7013dde9f.png?v=1770625062"},{"product_id":"ieej-avic2025d1","title":"A symmetrical STDP circuit suitable for low-power P-HCNM and time-series pattern recall in a fully connected hopfield network","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eD1\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eRyosuke Ohnuma (Nihon University), Yoshiki Sasaki (Nihon University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eAnalog circuits,Neuron,Hopfield network,VLSI,Spice simulation,Low voltage\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper presents a low-power neuromorphic architecture using a Pulse-type Hardware Chaotic Neuron Model (P-HCNM) and a symmetric \"Spike-Timing Dependent Plasticity\" (STDP) circuit for time-series pattern recall. While P-HCNMs enable energy-efficient brain-inspired computation, reducing the supply voltage lowers their firing frequency, making conventional STDP weight generation insufficient. To address this, we propose a symmetric STDP circuit employing a short-pulse generator based on falling-edge detection circuit using a current-mirror, ensuring stable and narrow gating suitable for low-voltage operation. A fully connected Hopfield network integrating the proposed STDP circuit and low-voltage P-HCNMs was designed and evaluated. Simulation results confirm reliable recall of timeseries patterns with significantly reduced power consumption, demonstrating the effectiveness of the proposed approach for compact, energy-efficient autonomous machine applications.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e69-72p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e656Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656272986351,"sku":"IEEJ-AVIC2025D1-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_f98a65a1-431f-42e1-9289-4f41523f42c4.png?v=1770625067"},{"product_id":"ieej-avic2025d2","title":"A study on feedback architecture for STDP learning in hierarchical neural networks using P-HCNM","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eD2\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eFuya Imamura (Nihon University), Yoshiki Sasaki (Nihon University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eSpiking neuron,VLSI,Analog electrical circuits,Hierarchical neural network,Spice simulation\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eIn recent years, research has been conducted on constructing networks capable of brain-inspired computing, which emulates the biological processing and recall abilities of external information. In the field of physiology, Spike Timing Dependent Plasticity (STDP)—a training rule that adjusts synaptic weights based on the timing difference between the firing of preceding and post neurons—has attracted significant attention. However, in previous studies, training signals were applied to both the preceding and post synaptic neurons to forcibly induce firing with a time difference. As a result, training was performed without relying on the natural timing of preceding and post synaptic firing. In this paper, we examine the architecture of a hierarchical neural network that enables training using an asymmetric STDP circuit, without the need to manually input timing differences to the preceding and post synaptic P-HCNMs in the hardware structure. As a result, we demonstrated that by introducing excitatory synaptic feedback connections from the preceding to post synaptic and from the post to preceding synaptic stages, it is possible to learn and recall 9 x 9 character image data, and perform classification of the input data.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e73-76p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e730Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656273641711,"sku":"IEEJ-AVIC2025D2-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_2e889db0-3729-4d79-9011-364501670a30.png?v=1770625073"},{"product_id":"ieej-avic2025d3","title":"A study on reducing processing time by narrowing down target vehicles in a BLE-based intersection collision prevention system","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eD3\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eHinata Murakoshi (Nihon University), Yoshiki Sasaki (Nihon University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eIntersection collision,Advanced driver assistance systems (ADAS),Global positioning system (GPS),Bluetooth low energy (BLE),Broadcast messaging over Bluetooth (BMoB)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eIn recent years, research has been conducted to detect vehicles approaching from blind spots to help prevent intersection collisions at poor visibility intersections. Previously, we proposed a system that can predict potential collisions by receiving data from the Global Positioning System (GPS) and transmitting it using Broadcast Messaging over Bluetooth (BMoB) via Bluetooth Low Energy (BLE). However, performing calculations on all BMoB signals received from the numerous BLE devices present in the surrounding environment significantly increases processing time. In this paper, we report on the development and evaluation of a system that estimates potential collisions only for \"Target\" vehicles deemed to pose a collision risk, by appending heading direction information to the BMoB data, and confirm that this approach enables a reduction in processing time. As a result, it was shown that the processing time can be reduced by approximately 10.71 ms for each additional \"Target\" vehicle excluded from the calculation. This demonstrates that, by filtering BMoB signals received from the many BLE devices in the vicinity to focus only on “Target” vehicles with a potential collision risk, the overall processing time of the program can be effectively reduced.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e77-80p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e907Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656275345647,"sku":"IEEJ-AVIC2025D3-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_01384b63-a7dd-42ee-8f88-5b256359d1cb.png?v=1770625078"},{"product_id":"ieej-avic2025d4","title":"A spike timing dependent plasticity learned feedback network in reservoir computing for timeseries pattern recognition","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eD4\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eAkinobu Yamaguchi (Nihon University), Yoshiki Sasaki (Nihon University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eReservoir computing,VLSI,Spiking neural network,Spike timing dependent plasticity\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eIn recent years, research into engineering applications of the biological brain's superior characteristics, such as its parallel processing capabilities, low power consumption, and compact implementation—has been gaining significant attention. Among these, Reservoir Computing (RC), which excels at time-series processing, has become a key focus. In our previous work, we constructed the reservoir layer of an RC system using the P-HCNM, a spiking neuron model built with analog electronic circuits used in Spiking Neural Networks (SNNs). However, to utilize the information generated by the reservoir layer, a readout layer must be designed. Applying the backpropagation algorithm, widely used in software-based neural networks, to SNNs is difficult. Therefore, in this study, we propose a feedback network Configuration for applying Spike Timing Dependent Plasticity (STDP)to the readout layer. We investigated whether both excitatory and inhibitory learning could be achieved based on the difference in output frequencies between the reservoir and output layers. The results demonstrate that the proposed network is capable of both excitatory and inhibitory learning depending on these frequency differences.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e81-84p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e528Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656275902703,"sku":"IEEJ-AVIC2025D4-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_023c1c4e-c373-4792-86c8-e1fcaa6621a8.png?v=1770625084"},{"product_id":"ieej-avic2025d5","title":"A study on yield improvement of low-voltage P-HCNM as spiking neuron circuit with latch-up countermeasures","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eD5\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eYoshiki Sasaki (Nihon University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003eVLSI,CMOS,Chaos,Pulse-type hardware neuron model(P-HCNM)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eThis paper describes a countermeasure against waveform generation defects in the IC implementation of a lowvoltage spiking neuron circuit using standard analog CMOS technology. Our goal is to realize artificial intelligence by reproducing brain-cell-like behavior with electronic circuits and hardware, with the aim of supplementing the workforce through autonomous robots. Previously, we proposed a spiking neuron model (P-HCNM) that can be constructed using only standard CMOS processes, but the yield of the separate-excitation model in IC implementation was below 50%. From our analysis, the failure was attributed to the activation of parasitic bipolar transistors caused by voltage increases due to bootstrapping in the circuit. To address this problem, we propose a modified circuit structure that incorporates a discharge path and a bias-current limiting mechanism. The proposed design was fabricated using a 0.18 um CMOS process and verified experimentally. The results demonstrate correct spike operation without latch-up and improved yield in the self-excitation model. Furthermore, simulation results show that the voltage bias error caused by the modification remains within acceptable limits.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e85-88p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e616Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656276295919,"sku":"IEEJ-AVIC2025D5-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_c693ab59-4129-4ad3-b7bf-25b3643d9d64.png?v=1770625090"},{"product_id":"ieej-avic2025d6","title":"A study on reservoir computing using a single P-HCNM with self-feedback","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ：\u003c\/strong\u003e国際会議\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No：\u003c\/strong\u003eD6\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名：\u003c\/strong\u003e【C】AVIC2025\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日：\u003c\/strong\u003e2025\/10\/20\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名：\u003c\/strong\u003eRyo Ono (Nihon University), Takeru Yonekawa (Nihon University), Takuto Yamaguchi (Nihon University), Katsutoshi Saeki (Nihon University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード：\u003c\/strong\u003ePhysical reservoir computing,Pulse-type hardware chaotic neuron model,Self-feedback,Temporal XOR task,Delay task\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語)：\u003c\/strong\u003eReservoir computing (RC), a computational framework derived from recurrent neural networks (RNNs), has attracted significant attention for its ease of implementation in physical systems. Because it is primarily due to the characteristic feature of the RC in which the connection weights of the reservoir layer are fixed, reducing the complexity of learning. In previous study, we investigated RC using a neural network of Pulse-type Hardware Chaotic Neuron Models (P-HCNMs), which are electronic circuit models that mimic biological neurons. However, the RC using electronic circuit models which mimic biological neurons have not yet been implemented in hardware. In this study, we implemented a single P-HCNM with self-feedback using discrete components and constructed a hardware-based reservoir computing system. To evaluate its performance, we have conducted a temporal XOR task and a Delay task, a typical benchmark in the RC. The system has achieved a low bit error rate of 4.7% and a high memory capacity of 1.07, demonstrating that the RC can be realized using a single PHCNM with feedback.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ：\u003c\/strong\u003e89-92p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別：\u003c\/strong\u003e英語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ：\u003c\/strong\u003e891Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 4","offer_id":47656276721903,"sku":"IEEJ-AVIC2025D6-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_bumontaikai_57f5c1a4-4be5-4668-bf28-b1611bf8753a.png?v=1770625095"}],"url":"https:\/\/ieej.bookpark.ne.jp\/collections\/kk-avic2025.oembed","provider":"電気学会 電子図書館","version":"1.0","type":"link"}