{"product_id":"ieej-28pm3-d-1","title":"シリコン貫通記録(TSV)と三次元集積化技術の研究開発動向","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ: \u003c\/strong\u003e部門大会\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No: \u003c\/strong\u003e28pm3-D-1\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名: \u003c\/strong\u003e第32回「センサ・マイクロマシンとその応用システム」シンポジウム論文集\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日: \u003c\/strong\u003e2015\/10\/21\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eタイトル(英語): \u003c\/strong\u003eRecent Research and Development of Through-Silicon Via (TSV) and 3D Integration Technologies \u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名: \u003c\/strong\u003e福島 誉史*，李 康旭，田中 徹，小柳 光正(東北大学)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード: \u003c\/strong\u003eSi 貫通配線,テンポラリー接合,ウェハ薄化,セルフアセンブリ,NCF \u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語): \u003c\/strong\u003eThis paper introduces the recent research and development of Through-Silicon Via (TSV) and 3D integrationtechnologies in order to solve upcoming limitation of Moore’s law scaling. In particular, from a reliability point ofview, via-last\/back-via technologies such as TSV liner dielectric formation, TSV barrier\/seed deposition, temporarybonding\/debonding, wafer thinning, assembly, and underfilling are discussed compared to conventionaltechnologies. \u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ: \u003c\/strong\u003e2,690 Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格440円\/会員価格220円） \/ A4 \/ 0","offer_id":46406864732399,"sku":"IEEJ-28pm3-D-1-PDF","price":440.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_6c4b4978-8459-4452-920d-a61c7a5759ab.png?v=1745150271","url":"https:\/\/ieej.bookpark.ne.jp\/products\/ieej-28pm3-d-1","provider":"電気学会 電子図書館","version":"1.0","type":"link"}