{"product_id":"ieej-ect14015","title":"A Feasibility Study of Robust and Low-Power Programmable Delay Elements Based on Neuron-MOS Mechanism","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ: \u003c\/strong\u003e研究会(論文単位)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e論文No: \u003c\/strong\u003eECT14015\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名: \u003c\/strong\u003e【C】電子・情報・システム部門 電子回路研究会\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日: \u003c\/strong\u003e2014\/01\/23\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eタイトル(英語): \u003c\/strong\u003eA Feasibility Study of Robust and Low-Power Programmable Delay Elements Based on Neuron-MOS Mechanism\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名: \u003c\/strong\u003e張 任遠(北陸先端科学技術大学院大学),金子 峰雄(北陸先端科学技術大学院大学)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名(英語): \u003c\/strong\u003eRenyuan Zhang(Japan Advanced Institute of Science and Technology),Mineo Kaneko(Japan Advanced Institute of Science and Technology)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード: \u003c\/strong\u003ePDE|Neuron-MOS|Low-Power|Robust\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(日本語): \u003c\/strong\u003eThe feasibility of programmable delay elements (PDEs) design based on Neuron-MOS mechanism is investigated in this work. By applying the capacitor coupling technology, the charging\/discharging current of a clock buffer can be digitally programmed to generate various switching delay without static power consumption. No any additional transistor is introduced into the charging\/discharging path, that reduces the performance fluctuation due to process variations for MOS transistors. Furthermore, a wide delay range could be available due to the simple charging\/discharging path. From the circuit simulation results, the delay change of proposed PDE is less than one third compared to that of the conventional PDE circuits. The Neuron-MOS-based PDE circuit achieves a delay change within 9.7% when the temperature fluctuates from 25 to 75 degree. In general, the suggested PDE circuit achieves better or fair performances over the robustness, power consumption and delay range.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語): \u003c\/strong\u003eThe feasibility of programmable delay elements (PDEs) design based on Neuron-MOS mechanism is investigated in this work. By applying the capacitor coupling technology, the charging\/discharging current of a clock buffer can be digitally programmed to generate various switching delay without static power consumption. No any additional transistor is introduced into the charging\/discharging path, that reduces the performance fluctuation due to process variations for MOS transistors. Furthermore, a wide delay range could be available due to the simple charging\/discharging path. From the circuit simulation results, the delay change of proposed PDE is less than one third compared to that of the conventional PDE circuits. The Neuron-MOS-based PDE circuit achieves a delay change within 9.7% when the temperature fluctuates from 25 to 75 degree. In general, the suggested PDE circuit achieves better or fair performances over the robustness, power consumption and delay range.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別: \u003c\/strong\u003e日本語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003ePDFファイルサイズ: \u003c\/strong\u003e1,363 Kバイト\u003c\/p\u003e","brand":"IEEJ-PDF","offers":[{"title":"PDFダウンロード（一般価格330円\/会員価格220円） \/ A4 \/ 6","offer_id":46362831028463,"sku":"IEEJ-ECT14015-PDF","price":330.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-PDF_a73f8f82-93e6-4b40-8939-0f28c86e38b0.png?v=1743640813","url":"https:\/\/ieej.bookpark.ne.jp\/products\/ieej-ect14015","provider":"電気学会 電子図書館","version":"1.0","type":"link"}