{"product_id":"ieej-rc13611-015","title":"実数値GA専用プロセッサの一方式","description":"\u003cp\u003e\u003cstrong\u003eカテゴリ: \u003c\/strong\u003e論文誌(論文単位)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eグループ名: \u003c\/strong\u003e【C】電子・情報・システム部門\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e発行日: \u003c\/strong\u003e2016\/11\/01\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eタイトル(英語): \u003c\/strong\u003eAn Architecture of Real Coded Genetic Algorithm Processor\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名: \u003c\/strong\u003e塚原　彰彦（東京電機大学大学院先端科学技術研究科），金杉　昭徳（東京電機大学大学院先端科学技術研究科）\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e著者名(英語): \u003c\/strong\u003eAkihiko Tsukahara (Graduate school of Science and Engineering, Tokyo Denki University), Akinori Kanasugi (Graduate school of Science and Engineering, Tokyo Denki University)\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eキーワード: \u003c\/strong\u003e遺伝的アルゴリズム，実数値GA，FPGA　　Generic Algorithm，Real Coded Generic Algorithm，FPGA\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e要約(英語): \u003c\/strong\u003eReal Coded Genetic Algorithm (RCGA) is one of evolutionary algorithm for handling real-valued vector. The RCGA is much better than conventional GA handling with bit strings as genotype. Various dedicated hardware for GA have been proposed for speedup or the applications of evolvable hardware. However, many of these hardware based on the bit strings GA or the compact GA. Therefore, there are few reports of RCGA hardware. In this paper, we propose an architecture of RCGA processor. The proposed processor conform to the Just Generation Gap (JGG) as a generation alternation model of RCGA. In addition, the processor is implemented the Real coded Ensemble Crossover (REX). One of the features of proposed processor is that the REX circuit can be implemented with small circuit scale because the circuit resources effectively shared such as arithmetic units. Furthermore, the second feature is to evaluate the offspring using by the soft macro CPU. Thus, the versatility is enhanced because the evaluation function that depend on problems can change by rewriting of software. Moreover, they are implemented in parallel for speeding up. The proposed processor is expected in embedded field applications because of it can be implemented in one chip FPGA.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌: \u003c\/strong\u003e\u003ca href=\"\/products\/ieej-rc13611\"\u003e電気学会論文誌C（電子・情報・システム部門誌） Vol.136 No.11 （2016） 特集：電気関係学会関西連合大会\u003c\/a\u003e\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e本誌掲載ページ: \u003c\/strong\u003e1586-1595 p\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e原稿種別: \u003c\/strong\u003e論文／日本語\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003e電子版へのリンク: \u003c\/strong\u003e\u003ca target=\"_blank\" href=\"https:\/\/www.jstage.jst.go.jp\/article\/ieejeiss\/136\/11\/136_1586\/_article\/-char\/ja\/\"\u003ehttps:\/\/www.jstage.jst.go.jp\/article\/ieejeiss\/136\/11\/136_1586\/_article\/-char\/ja\/\u003c\/a\u003e\u003c\/p\u003e","brand":"IEEJ-P10","offers":[{"title":"冊子印刷（一般価格770円\/会員価格550円） \/ A4 \/ 10","offer_id":46349972111599,"sku":"IEEJ-RC13611-015-PRT","price":770.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0718\/9512\/2159\/files\/IEEJ-RC13611_fa73b7d4-8b73-42a2-87de-af0cecc601b9.png?v=1743166586","url":"https:\/\/ieej.bookpark.ne.jp\/products\/ieej-rc13611-015","provider":"電気学会 電子図書館","version":"1.0","type":"link"}