High-speed a four-armed bandit problem solving IC in CMOS 180 nm technology

カテゴリ：国際会議

論文No：A5

グループ名：【C】AVIC2025

発行日：2025/10/20

著者名：Tomoki Furuta (Meiji University), Rin Tsuboi (Meiji University), Kawori Sekine (Meiji University), Kazuyuki Wada (Meiji University), Shinsuke Hara (National Institute of Information and Communications Technology), Satoru Tanoi (National Institute of Information and Communications Technology), Akifumi Kasamastu (National Institute of Information and Communications Technology)

キーワード：Multi-armed bandit problem,Machine learning,Integrated circuit,CMOS,CML latch

要約(英語)：This study expands a previously developed GHzband two-armed bandit (2AB) problem solving IC into a fourarmed bandit (4AB) problem-compatible circuit, thereby enabling learning from a wider range of options to select the optimal one. In addition to modifying the timing chart and redesigning the component values of the current-mode-logic (CML) latch, we introduced a multiplexer control signal generation circuit and optimized its device parameters to achieve high-speed operation. Simulation results demonstrated that the proposed circuit successfully learns the optimal slot machine at a system clock frequency of 3 GHz, confirming its effectiveness and high-speed performance.

本誌掲載ページ：21-24p

原稿種別：英語

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