A 728 mV and 23.4 ppm/degC voltage reference using parasitic diode biasing for temperature compensation in 28 nm FD-SOI technology

カテゴリ：国際会議

論文No：C1

グループ名：【C】AVIC2025

発行日：2025/10/20

著者名：Maxime Guillot (Universite de Bordeaux), Yann Deval (Universite de Bordeaux), Herve Lapuyade (Universite de Bordeaux), Francois Rivet (Universite de Bordeaux)

キーワード：Voltage reference,PTAT,CTAT,Back-Gate biasing,Thermal dependency,FD-SOI,Parasitic diode biasing

要約(英語)：This paper presents a new voltage reference circuit developed in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The proposed voltage reference uses the combination of PTAT and CTAT voltages, along with the implementation of parasitic diode biasing. This biasing approach modifies the behavior of transistors, reducing their thermal dependency. The resulting circuit delivers an output voltage of 728 mV with a temperature coefficient of 23.4 ppm/degC across a temperature range of -50 degC to 150 degC and under a 1.8 V supply.

本誌掲載ページ：45-48p

原稿種別：英語

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