A symmetrical STDP circuit suitable for low-power P-HCNM and time-series pattern recall in a fully connected hopfield network

カテゴリ：国際会議

論文No：D1

グループ名：【C】AVIC2025

発行日：2025/10/20

著者名：Ryosuke Ohnuma (Nihon University), Yoshiki Sasaki (Nihon University)

キーワード：Analog circuits,Neuron,Hopfield network,VLSI,Spice simulation,Low voltage

要約(英語)：This paper presents a low-power neuromorphic architecture using a Pulse-type Hardware Chaotic Neuron Model (P-HCNM) and a symmetric "Spike-Timing Dependent Plasticity" (STDP) circuit for time-series pattern recall. While P-HCNMs enable energy-efficient brain-inspired computation, reducing the supply voltage lowers their firing frequency, making conventional STDP weight generation insufficient. To address this, we propose a symmetric STDP circuit employing a short-pulse generator based on falling-edge detection circuit using a current-mirror, ensuring stable and narrow gating suitable for low-voltage operation. A fully connected Hopfield network integrating the proposed STDP circuit and low-voltage P-HCNMs was designed and evaluated. Simulation results confirm reliable recall of timeseries patterns with significantly reduced power consumption, demonstrating the effectiveness of the proposed approach for compact, energy-efficient autonomous machine applications.

本誌掲載ページ：69-72p

原稿種別：英語

PDFファイルサイズ：656Kバイト