A study on yield improvement of low-voltage P-HCNM as spiking neuron circuit with latch-up countermeasures

カテゴリ：国際会議

論文No：D5

グループ名：【C】AVIC2025

発行日：2025/10/20

著者名：Yoshiki Sasaki (Nihon University)

キーワード：VLSI,CMOS,Chaos,Pulse-type hardware neuron model(P-HCNM)

要約(英語)：This paper describes a countermeasure against waveform generation defects in the IC implementation of a lowvoltage spiking neuron circuit using standard analog CMOS technology. Our goal is to realize artificial intelligence by reproducing brain-cell-like behavior with electronic circuits and hardware, with the aim of supplementing the workforce through autonomous robots. Previously, we proposed a spiking neuron model (P-HCNM) that can be constructed using only standard CMOS processes, but the yield of the separate-excitation model in IC implementation was below 50%. From our analysis, the failure was attributed to the activation of parasitic bipolar transistors caused by voltage increases due to bootstrapping in the circuit. To address this problem, we propose a modified circuit structure that incorporates a discharge path and a bias-current limiting mechanism. The proposed design was fabricated using a 0.18 um CMOS process and verified experimentally. The results demonstrate correct spike operation without latch-up and improved yield in the self-excitation model. Furthermore, simulation results show that the voltage bias error caused by the modification remains within acceptable limits.

本誌掲載ページ：85-88p

原稿種別：英語

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