Advanced Power Panel-level Packaging using Chip Embedded and Power Chiplet Technology for AI and Vehicles

カテゴリ：部門大会

論文No：TC12-4

グループ名：【C】2025年電気学会電子・情報・システム部門大会

発行日：2025/8/20

タイトル(英語)：Advanced Power Panel-level Packaging using Chip Embedded and Power Chiplet Technology for AI and Vehicles

著者名：Z Seng Roi Htoi（アオイ電子株式会社）,Takao Katsuhiro（アオイ電子株式会社）,Iwabu Koji（アオイ電子株式会社）,Suzuki Takashi（アオイ電子株式会社）,Aizawa Yoshiaki（アオイ電子株式会社）

著者名(英語)： Seng Roi Htoi Z (AOI ELECTRONICS),Katshiro Takao (AOI ELECTRONICS),Koji Iwabu (AOI ELECTRONICS),Takashi Suzuki (AOI ELECTRONICS),Yoshiaki Aizawa (AOI ELECTRONICS)

キーワード：パネルレベルパッケージ,チップエンベッド,パワーチップレット,AIとデータセンタ,車両,Panel-level Package,Chip Embedded,Power Chiplet,AI/ Data center,Vehicle

要約(日本語)：Recently, power applications such as AI/data centers and EVs, power distribution losses due to wiring resistance and heat generation devices have become a major concern as power supply output current increases. We are focusing on the development of power packaging using chip embedded technology based on 300mm square panel-level processes. We have developed several chip-embedded packages such as GaN DC-DC half-bridge modules and SiC sub-module packages featuring ultra-thinness, low resistance, low inductance, and high heat dissipation, using direct copper plating on both sides of the chip and power chiplet technology to connect multiple chips in parallel.  In this report, we present several power application development case studies through prototyping and reliability test results.

本誌掲載ページ：488-493p

原稿種別：英語

PDFファイルサイズ：927Kバイト