Ultra Wafer Thinning Technology for 3D Integration

カテゴリ: 部門大会

論文No: MC5-3

グループ名: 【C】平成25年電気学会電子・情報・システム部門大会講演論文集

発行日: 2013/09/04

タイトル(英語): Ultra Wafer Thinning Technology for 3D Integration

著者名: Young Suk Kim (東京大学)

著者名(英語): Young Suk Kim (The Univ. of Tokyo)

キーワード: 薄化|Thinning

要約(日本語): Stacking at the wafer level significantly increases the processing throughput, and low aspect ratio and “bumpless” TSVs give excellent contact yield as well as lower via stress. There need further optimization of total thickness variation (TTV) in the stacking module. This paper describes high resolution grinding process for ultra-thinning using DGP8761 (DISCO) with in-situ thickness measurement (Auto-TTV, NCG = non-contact gauge). Wafer thinning effect for logic devices on mobility, gettering, and switching charge characteristics are discussed.

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