Digital Foreground Calibration for SAR-ADCs with Redundancy Implementation

カテゴリ: 部門大会

論文No: SS2-3

グループ名: 【C】平成30年電気学会電子・情報・システム部門大会プログラム

発行日: 2018/09/05

タイトル(英語): Digital Foreground Calibration for SAR-ADCs with Redundancy Implementation

著者名: Mishiro Taro(Tokyo University of Science),Hyogo Akira(Tokyo University of Science),Matsuura Tatsuji(Tokyo University of Science),Kishida Ryo(Tokyo University of Science)

著者名(英語): Taro Mishiro|Akira Hyogo|Tatsuji Matsuura|Ryo Kishida

キーワード: SAR-ADC|foreground calibration|redundancy|DAC mismatch

要約(日本語): Successive-approximation A/D converter (SAR-ADC) compares input voltages with the voltages made by a DAC composed of capacitor arrays. SAR-ADC does not use OP-amps. Therefore, it has the advantages of low-power consumption and suitability to fine processes. However, the linearity of the ADC decreases when the fabricated binary weighted capacitors have mismatches.This study proposes to calibrate SAR-ADC using output digital codes. It is possible to improve accuracy by estimating the actual bit weight (changed due to capacitor mismatches), and by correcting the digital output using the actual bit weight. As a result, conventional SAR-ADC with capacitor mismatches has large quantization error, whereas the proposed calibrated ADC has less quantization error which varies within about ±1/2LSB.

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