A Feasibility Study of Robust and Low-Power Programmable Delay Elements Based on Neuron-MOS Mechanism

カテゴリ: 研究会(論文単位)

論文No: ECT14015

グループ名: 【C】電子・情報・システム部門 電子回路研究会

発行日: 2014/01/23

タイトル(英語): A Feasibility Study of Robust and Low-Power Programmable Delay Elements Based on Neuron-MOS Mechanism

著者名: 張 任遠(北陸先端科学技術大学院大学),金子 峰雄(北陸先端科学技術大学院大学)

著者名(英語): Renyuan Zhang(Japan Advanced Institute of Science and Technology),Mineo Kaneko(Japan Advanced Institute of Science and Technology)

キーワード: PDE|Neuron-MOS|Low-Power|Robust

要約(日本語): The feasibility of programmable delay elements (PDEs) design based on Neuron-MOS mechanism is investigated in this work. By applying the capacitor coupling technology, the charging/discharging current of a clock buffer can be digitally programmed to generate various switching delay without static power consumption. No any additional transistor is introduced into the charging/discharging path, that reduces the performance fluctuation due to process variations for MOS transistors. Furthermore, a wide delay range could be available due to the simple charging/discharging path. From the circuit simulation results, the delay change of proposed PDE is less than one third compared to that of the conventional PDE circuits. The Neuron-MOS-based PDE circuit achieves a delay change within 9.7% when the temperature fluctuates from 25 to 75 degree. In general, the suggested PDE circuit achieves better or fair performances over the robustness, power consumption and delay range.

要約(英語): The feasibility of programmable delay elements (PDEs) design based on Neuron-MOS mechanism is investigated in this work. By applying the capacitor coupling technology, the charging/discharging current of a clock buffer can be digitally programmed to generate various switching delay without static power consumption. No any additional transistor is introduced into the charging/discharging path, that reduces the performance fluctuation due to process variations for MOS transistors. Furthermore, a wide delay range could be available due to the simple charging/discharging path. From the circuit simulation results, the delay change of proposed PDE is less than one third compared to that of the conventional PDE circuits. The Neuron-MOS-based PDE circuit achieves a delay change within 9.7% when the temperature fluctuates from 25 to 75 degree. In general, the suggested PDE circuit achieves better or fair performances over the robustness, power consumption and delay range.

原稿種別: 日本語

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