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Velocity Control Based on a Wide Range of Velocity Estimation in FPGA

Velocity Control Based on a Wide Range of Velocity Estimation in FPGA

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カテゴリ: 研究会(論文単位)

論文No: IIC11066

グループ名: 【D】産業応用部門 産業計測制御研究会

発行日: 2011/03/08

タイトル(英語): Velocity Control Based on a Wide Range of Velocity Estimation in FPGA

著者名: ナンダヤパ アルファロ マヌエル デ ジェスッス (長岡技術科学大学),ミッサンティスク チャワリット(長岡技術科学大学),大石 潔(長岡技術科学大学)

著者名(英語): Nandayapa Alfaro Manuel de Jesus (Nagaoka University of Technology),Mitsantisuk Chowarit(Nagaoka University of Technology),Ohishi Kiyoshi(Nagaoka University of Technology)

キーワード: 速度推定法|外乱オブザーバ|モーションコントロール|FPGA|ロボティクス|ボールねじ|Velocity estimation|Disturbance Observer|Motion Control|FPGA|Robotic|Ball screw

要約(日本語): In the motion control, the controllers based on Field Programmable Gate Array (FPGA) have increase in recent years due the short sampling time. The velocity estimation methods that are implemented commonly are M and T methods. The proposed velocity estimation method reduces the calculation without dividers and avoid the low resolution with short sampling time. In addition, the velocity estimation has a high performance in a wide range. The implementation in the FPGA has low cost computationally and high speed of calculation. The traditional methods present some difficulties to program in the FPGA due to divider implementation. The validity of the proposed method was tested in a velocity controller based on the disturbance observer.

要約(英語): In the motion control, the controllers based on Field Programmable Gate Array (FPGA) have increase in recent years due the short sampling time. The velocity estimation methods that are implemented commonly are M and T methods. The proposed velocity estimation method reduces the calculation without dividers and avoid the low resolution with short sampling time. In addition, the velocity estimation has a high performance in a wide range. The implementation in the FPGA has low cost computationally and high speed of calculation. The traditional methods present some difficulties to program in the FPGA due to divider implementation. The validity of the proposed method was tested in a velocity controller based on the disturbance observer.

原稿種別: 日本語

PDFファイルサイズ: 1,551 Kバイト

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