Through-Silicon Via (TSV) drilling using femtosecond Bessel beams at 1.5 micron wavelength

カテゴリ: 研究会(論文単位)

論文No: OQD14010

グループ名: 【C】電子・情報・システム部門 光・量子デバイス研究会

発行日: 2014/03/07

タイトル(英語): Through-Silicon Via (TSV) drilling using femtosecond Bessel beams at 1.5 micron wavelength

著者名: He Fei(理化学研究所/中国科学院上海光学精密機械研究所),Wan Zhaohui(中国科学院上海光学精密機械研究所),Zeng Bin(中国科学院上海光学精密機械研究所),Cheng Ya(中国科学院上海光学精密機械研究所),杉岡 幸次(理化学研究所)

著者名(英語): Fei He(RIKEN/SIOM),Zhaohui Wan(SIOM),Bin Zeng(SIOM),Ya Cheng(SIOM),Koji Sugioka(RIKEN)

キーワード: Femtosecond laser|Bessel beam|Through Si via|Drilling

要約(日本語): Currently, fabrication of vertical connections through silicon substrates is a significant challenge in three-dimensional (3D) integrated circuits manufacturing. In particular, high aspect ratio, taper-free trough vias with micron ~ tens micron diameters in silicon chips are critical constructions for vertical miniaturization. We report on drilling though vias in silicon chips by use of 1.5 μm femtosecond Bessel beams, which is transparent to Si, in air and AgNO3 solutions, respectively. Compared with conventional fabrication methods using Gaussian beams, our technique allows for high performance hole drilling with taperless fabrication and without sample translation, which can be potentially used for future 3D packages and 3D integration of silicon chips.

要約(英語): Currently, fabrication of vertical connections through silicon substrates is a significant challenge in three-dimensional (3D) integrated circuits manufacturing. In particular, high aspect ratio, taper-free trough vias with micron ~ tens micron diameters in silicon chips are critical constructions for vertical miniaturization. We report on drilling though vias in silicon chips by use of 1.5 μm femtosecond Bessel beams, which is transparent to Si, in air and AgNO3 solutions, respectively. Compared with conventional fabrication methods using Gaussian beams, our technique allows for high performance hole drilling with taperless fabrication and without sample translation, which can be potentially used for future 3D packages and 3D integration of silicon chips.

原稿種別: 日本語

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