アーキテクチャを考慮した複数エラーの差分推定に基づくフォールト解析とその評価

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2012/12/01

タイトル(英語): Architecture Aware Fault Analysis Based on Differential Presumption for Multiple Errors and its Evaluation

著者名: 小野　みどり（名城大学／独立行政法人科学技術振興機構，CREST），勝部　真人（名城大学），汐崎　充（独立行政法人科学技術振興機構，CREST／立命館大学），藤野　毅（独立行政法人科学技術振興機構，CREST／立命館大学），吉川　雅弥（名城大学／独立行政法人科学技術振興機構，CREST）

著者名(英語): Midori Ono (Meijo University/JST, CREST), Masato Katsube (Meijo University), Mitsuru Shiozaki (JST, CREST/Ritsumeikan University), Takeshi Fujino (JST, CREST/Ritsumeikan University), Masaya Yoshikawa (Meijo University/JST, CREST)

キーワード: フォールト解析攻撃，差分故障解析，暗号回路構成，差分推定，複数エラー，AES暗号　　Fault analysis attack，Differential fault analysis，Cryptographic circuit architecture，Differential presumption，Multiple errors，Advanced Encryption Standard

要約(英語): Recently, the number of electronic devices handling confidential information has increased. In these devices, cryptographic circuits are applied to protect the confidential information. It has been sufficiently confirmed that the decryption of the encryption standards used in cryptographic circuits is computationally impossible. However, it was recently reported that when a theoretically safe encryption algorithm was embedded in the hardware, confidential information could be illegally specified by fault analysis attacks. Here, fault analysis attacks specify the secret keys by intentionally generating a fault during the encryption processing and by comparing the fault and normal cases. Almost all previous studies have strictly constraints related to the number of faults and the position of faults. Therefore, this study proposes a new fault analysis attack which has no constraint for the number of faults and considers the architecture. Experimental results using FPGA show the validity of the proposed attack.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.132 No.12 （2012） 特集：電気関係学会東海支部連合大会

本誌掲載ページ: 1888-1896 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/132/12/132_1888/_article/-char/ja/