積層構造DTMOS（スタック型DTMOS）の検討

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2012/12/01

タイトル(英語): Design Technology of Stacked Type DTMOS

著者名: 廣島　佑（大井電気（株）），小玉　貴大（日本プロセス（株）），渡辺　重佳（湘南工科大学工学部情報工学科）

著者名(英語): Yu Hiroshima (Oi Electric Co., Ltd.), Takahiro Kodama (Japan Process Development Co., Ltd.), Shigeyoshi Watanabe (Department of Information Science, Shonan Institute of Technology)

キーワード: FinFET，積層構造，DTMOS，パターン面積，システムLSI　　FinFET，stacked structure，DTMOS，pattern area，system LSI

要約(英語): Stacked type DTMOS which enables to realize both high-speed low-power characteristics of FinFET type DTMOS and small pattern area of stacked transistor has been newly proposed. The delay time of substrate of stacked type DTMOS can be reduced to less than 10% compared with that of conventional FinFET type DTMOS by using the sidewall connection between gate and substrate. By using stacked structure of NMOS with (110) substrate on PMOS with (100) substrate high speed performance with the optimized mobility value can be realized without sacrificing the pattern area. Furthermore, the pattern area of inverter/NAND circuit, LSI for communication and DRAM buffer circuit with stacked type DTMOS has been compared with that of conventional FinFET type DTMOS. Newly proposed stacked type DTMOS is a promising candidate for realizing high performance system LSI such as the microprocessor of GHz operation.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.132 No.12 （2012） 特集：電気関係学会東海支部連合大会

本誌掲載ページ: 1927-1933 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/132/12/132_1927/_article/-char/ja/