ΔΣ型分数分周PLLのセルフディザリング手法の検討

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2013/02/01

タイトル(英語): A Study of Self-Dithering for ΔΣ Fractional-N PLL

著者名: 加藤　勇児（青山学院大学大学院理工学研究科理工学専攻），井岡　惠理（青山学院大学大学院理工学部電気電子工学科），松谷　康之（青山学院大学大学院理工学部電気電子工学科）

著者名(英語): Yuji Kato (Graduate School of Science and Engineering, Aoyama Gakuin University), Eri Ioka (College of science and engineering, Aoyama Gakuin University), Yasuyuki Matsuya (College of science and engineering, Aoyama Gakuin University)

キーワード: PLL，分数分周方式，ΔΣモジュレータ，リミットサイクル発振，ディザ　　PLL，Fractional-N，ΔΣ modulator，Limit-cycle，Dithering

要約(英語): The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.133 No.2 （2013） 特集：省電力時代の電子回路技術

本誌掲載ページ: 234-238 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/133/2/133_234/_article/-char/ja/