暗号ハードウェアのゲートレベル設計工程における電力解析攻撃に対する脆弱性評価手法

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2013/05/01

タイトル(英語): A Vulnability Evaluation Method against Power Analisys Attack on Gate-level Design Phase

著者名: 浅井　稔也（名城大学／独立行政法人科学技術振興機構,CREST），汐崎　充（独立行政法人科学技術振興機構,CREST／立命館大学），藤野　毅（独立行政法人科学技術振興機構,CREST／立命館大学），吉川　雅弥（名城大学／独立行政法人科学技術振興機構,CREST）

著者名(英語): Toshiya Asai (Meijo University/JST, CREST), Mitsuru Shiozaki (JST, CREST/Ritsumeikan University), Takeshi Fujino (JST, CREST/Ritsumeikan University), Masaya Yoshikawa (Meijo University/JST, CREST)

キーワード: 暗号回路，脆弱性，電力解析攻撃，重回帰分析，標準暗号AES　　Cryptography circuit，Vulnerability，Power analysis attack，Multiple regression analysis，Advanced Encryption Standard

要約(英語): Electronic devices handling confidential information, such as IC cards, are secured by encrypting data. The encryption standard, which has been widely diffused in recent years, is certified that its decryption is computationally impossible. However, although an encryption algorithm is theoretically secured, when the algorithm is incorporated into hardware, confidential information about the algorithm could be improperly specified by analyzing power consumption that is generated during cipher processing. Therefore, when an encryption algorithm is incorporated into hardware, it is important to evaluate the resistance against power analysis attacks in the design stages. This paper proposes a new vulnerability evaluation for power analysis attacks. The proposed method can not only achieve a high-speed, highly accurate verification but also quantitatively evaluates a weak part. Experimental results prove the validity of the proposed tamper resistant analysis method.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.133 No.5 （2013） 特集：新たな産業への応用が進む無線通信技術

本誌掲載ページ: 947-956 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/133/5/133_947/_article/-char/ja/