周波数領域における部分鍵推定を用いたハイブリッド電力解析攻撃とその評価

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2013/07/01

タイトル(英語): Subkey Driven Hybrid Power Analysis Attack in Frequency Domain against Cryptographic LSIs and its Evaluation

著者名: 佐藤　隆亮（名城大学），松島　大祐（名城大学），汐崎　充（立命館大学／独立行政法人科学技術振興機構,CREST），藤野　毅（立命館大学／独立行政法人科学技術振興機構,CREST），吉川　雅弥（名城大学／独立行政法人科学技術振興機構,CREST）

著者名(英語): Ryusuke Satoh (Meijo University), Daisuke Matsushima (Meijo University), Mitsuru Shiozaki (Ritsumeikan University/JST, CREST), Takeshi Fujino (Ritsumeikan University/JST, CREST), Masaya Yoshikawa (Meijo University/JST, CREST)

キーワード: ハードウェアセキュリティ，サイドチャネル攻撃，電力解析攻撃，周波数領域，暗号LSI　　Hardware security，Side-channel attack，Power analysis attack，Frequency domain，Cryptographic LSI

要約(英語): Recently, the threat level of power analysis attacks has been raised. Power analysis attacks acquire confidential information from cryptographic circuits that are embedded in hardware, such as credit and cash cards, by analyzing their power consumption. Therefore, it is important to secure resistance against power analysis attacks. This study proposes a new power analysis attack method that can be used to improve the efficiency of the resistance evaluation of cryptographic LSI. The proposed method performs power analysis not in the conventional time domain but in the frequency domain. Moreover, it uses a partial key that is specified through the use of conventional power analysis attack to estimate other partial keys. Compared with resistance evaluation that uses typical attack methods, the proposed method reduces the computational amount required for resistance evaluation greatly while maintaining the attack accuracy. The validity of the proposed method is verified through evaluation experiments performed with the use of a cryptographic circuit implemented on FPGA.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.133 No.7 （2013） 特集：平成24 年電気学会電子・情報・システム部門大会

本誌掲載ページ: 1322-1330 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/133/7/133_1322/_article/-char/ja/