暗号ハードウェア実装回路のサイドチャネル攻撃対策評価

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2014/12/01

タイトル(英語): Side-channel Attack Countermeasure Evaluation of Cryptographic Hardware Implementation Circuit

著者名: 浅井　稔也（名城大学／（独）科学技術振興機構, CREST），旭　健作（名城大学／（独）科学技術振興機構, CREST），汐崎　充（（独）科学技術振興機構, CREST／立命館大学），藤野　毅（（独）科学技術振興機構, CREST／立命館大学），吉川　雅弥（名城大学／（独）科学技術振興機構, CREST）

著者名(英語): Toshiya Asai (Meijo University/JST, CREST), Kensaku Asahi (Meijo University/JST, CREST), Mitsuru Shiozaki (JST, CREST/Ritsumeikan University), Takeshi Fujino (JST, CREST/Ritsumeikan University), Masaya Yoshikawa (Meijo University/JST, CREST)

キーワード: サイドチャネル攻撃，AES，LSI，対策　　Side Channel Attack，AES，LSI，Countermeasure

要約(英語): The encryption standard, which has been widely used, is computationally secured. It is reported that encryption standard becomes vulnerable against side-channel attacks (SCA) when it was incorporated in hardware. Therefore, various measures against SCA have been proposed. Evaluation and verification of vulnerability against SCA are the most important priority for the measures. This paper proposes a new method for efficient evaluation of SCA measures on design phase of LSI. The proposed method introduces event-modeling simulation and clustering technique in order to achieve highly efficient evaluation. Moreover, the proposed method can detect the vulnerable cells on designing phase of LSI. Experimental results using 018um CMOS standard cell library prove the validity of the proposed method.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.134 No.12 （2014） 特集：電気関係学会東海支部連合大会

本誌掲載ページ: 1767-1774 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/134/12/134_1767/_article/-char/ja/