神経信号取得用多チャンネル低雑音低消費電力増幅器の周波数特性ばらつき補償

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2015/01/01

タイトル(英語): Multi Channel Low-Noise Low-Power Amplifier for Neural Signal Acquisition

著者名: 安田　陽平（慶應義塾大学大学院理工学研究科総合デザイン工学専攻），中野　誠彦（慶應義塾大学理工学部電子工学科）

著者名(英語): Yohei Yasuda (Department of Integrated Design Engineering, Graduate School of Science and Technology, The University of Keio), Nobuhiko Nakano (Department of Electronics and Electrical Engineering, School of Science and Technology, The University of Keio)

キーワード: CMOS LSI，低雑音低消費電力設計，生体信号，神経信号増幅器　　CMOS LSI，cutoff frequency variation，low-noise low-power design，bio-signal，neural signal amplifier

要約(英語): This paper describes a low-noise and low-power spike neural signal amplifier design that has cutoff frequency compensation between the channels and chips variations. The variation of the frequency characteristics of amplifiers should be minimized among the channels and chips. That is a requirement to do the statistical correlation analysis from a neuroscience point of view. Our design includes the adjustable cutoff frequency using 4 bit variable capacitance. After the compensation the variation of the cutoff frequency was reduced to -0.4kHz to +0.3kHz from -1.1kHz to +3.6kHz that is the value of before trimming under the condition of the target cutoff frequency is 10kHz. We designed a multi neural signal amplifier using ROHM 0.18µm CMOS process. The designed neural amplifier has the capacitive coupled differential input to reject large dc offsets generated at the electrode-tissue interface and to avoid the large common mode noise. To achieve the high energy efficiency with low noise to observe the few tens of µV order spike signal, the MOS transistors in OTA are operated at subthreshold region and combined with low pass filter that consumes less than a hundred nW. The amplifier yielded a midband gain of 37.9dB and the input-referred noise was measured to be 3.76µVrms while consuming 4.30µW with a ±0.9V power supply. These results corresponding to Noise Efficiency Factor (NEF)=2.23 that are close to the value of the limit using a single differential OTA by CMOS process.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.135 No.1 （2015） 特集：インタフェース関連アナログ電子回路技術

本誌掲載ページ: 2023/02/11 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/135/1/135_2/_article/-char/ja/