分周比に依存しないデューティ比50%の可変分周器とそのPLLへの応用

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2016/01/01

タイトル(英語): A Programmable Divider with 50% Duty Cycle Unrelated to Dividing Cycle and its Application to PLL

著者名: 原田　裕二郎（東海大学大学院産業工学研究科），矢原　充敏（東海大学福岡短期大学），松本　欣也（東海大学大学院産業工学研究科），藤本　邦昭（東海大学大学院産業工学研究科）

著者名(英語): Yujiro Harada (Graduate School of Industrial Engineering, Tokai University), Mitsutoshi Yahara (Tokai University Fukuoka Junior College), Kinya Matsumoto (Graduate School of Industrial Engineering, Tokai University), Kuniaki Fujimoto (Graduate School of Industrial Engineering, Tokai University)

キーワード: 可変分周器，デューティ比，位相同期ループ　　programmable divider，duty cycle，phase locked loop

要約(英語): Recently, a signal processing using positive and negative edges of clock is used by memory and various digital devices to improve performance of digital circuits. In a signal processing using double edges, 50% duty cycle of an output signal of clock generator is an important factor. In this paper, we propose the programmable divider which always we obtain the output signal of 50% duty cycle unrelated to the dividing ratio. The circuit configuration of this divider is very simple, and the operation is stable regardless of the increase in the division ratio. Also, when the proposed divider was included in the dividing ratio changeable-digital phase locked loop (DC-PLL), the output signal is always kept to 50% duty cycle regardless of the frequency of input signal. In experimental results using an FPGA, we confirmed that this DC-PLL has the expected characteristics for phase error, lock-in range, and initial pull-in.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.136 No.1 （2016） 特集：電子回路関連技術

本誌掲載ページ: 2023/02/07 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/136/1/136_2/_article/-char/ja/