ブロック構造パルスニューラルネットワークにおける誤差逆伝播法のハードウェア実装

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2016/08/01

タイトル(英語): A Hardware Implementation of Back Propagation for Block-based Pulsed Neural Networks

著者名: 萩尾　賢太（千葉大学），小圷　成一（千葉大学），岡本　卓（千葉大学）

著者名(英語): Kenta Hagio (Chiba University), Seiichi Koakutsu (Chiba University), Takashi Okamoto (Chiba University)

キーワード: 進化型ハードウェア，FPGA，ニューラルネットワーク，学習，ブロック構造パルスニューラルネットワーク，誤差逆伝播法　　Evolvable Hardware，FPGA，Neural Network，Learning，Block-Based Pulsed Neural Network，Back Propagation

要約(英語): Evolvable Hardware (EHW) is reconfigurable hardware which can adopt to unknown new environments. EHW can be implemented combining learning networks such as Neural Networks (NNs) and programmable devices such as FPGA (Field Programmable Gate Array). As such research of EHW, Block-Based Neural Networks (BBNNs) have been proposed. BBNNs have simplified network structures and have been attracting attention with their ease of hardware implementation. In particular, Block-Based Pulsed Neural Networks (BBPNNs) which adopt a pulsed neuron model instead of an analogue neuron model in BBNNs have been proposed in order to solve the problem that BBNNs use many multiplier circuits and require large scale hardware resources for implementation. In addition, applying Back Propagation (BP) which is common learning algorithm of NNs to BBPNNs has been proposed. In this paper, we propose two approximation methods in order to reduce hardware resources which are necessary to apply BP to BBPNNs. In the proposed methods, we approximate input values and derivative values of activation function in BP. Results of computational experiments indicate the validity of the proposed methods.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.136 No.8 （2016） 特集Ⅰ：知能メカトロニクス分野と連携する知覚情報技術　特集Ⅱ：国際会議ICESS 2015

本誌掲載ページ: 1230-1236 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/136/8/136_1230/_article/-char/ja/