縦型トランジスタ構造を用いた階層積層型Fe-FET NAND/NANDアレイの提案とそのロジックLSIへの適用検討

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2017/05/01

タイトル(英語): Proposal of Hierarchical Stacked Type Fe-FET NAND/NAND Array and its Application to Logic LSI

著者名: 横田　智広（（株）DNPデータテクノ），渡辺　重佳（湘南工科大学工学部情報工学科）

著者名(英語): Tomohiro Yokota (DNP Data Techno Co. Ltd.), Shigeyoshi Watanabe (Department of Information Science, Shonan Institute of Technology)

キーワード: NAND型メモリ，Fe-FET，縦型トランジスタ構造，NANDアレイ，論理LSI，再構成可能　　NAND type memory，Fe-FET，vertical transistor，NAND array，logic LSI，reconfigurable architecture

要約(英語): The reduction of fabrication cost without reduction of transistor size is main target for future logic LSI. Previously stacked type Fe-FET NAND/NAND array with the single circuit block architecture for logic circuit had been proposed for this target. In this paper vertical hierarchical stacked type Fe-FET NAND/NAND array and its application to logic LSI have been newly proposed. The feature of the proposed scheme is multiple stacked circuit blocks architecture which operates independently. Compared with the single circuit block architecture the fabrication cost per circuit can be reduced to 36% using 16 stages circuit blocks without sacrificing high speed and low power characteristics. The proposed scheme is one of the most promising candidates for realizing low cost high speed future logic LSI.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.137 No.5 （2017）

本誌掲載ページ: 678-686 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/137/5/137_678/_article/-char/ja/