部分最適化を用いたコンパレータ回路の自動設計の高速化

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2018/01/01

タイトル(英語): High-speed Automatic Design of Comparator Circuit Using Divided Circuit Optimization

著者名: 髙井　伸和（群馬大学　大学院理工学府），吉澤　慧（群馬大学　大学院理工学府），鈴木　研人（群馬大学　大学院理工学府），菅原　誉士紀（群馬大学　大学院理工学府）

著者名(英語): Nobukazu Takai (Faculty of Science and Technology, Gunma University), Satoshi Yoshizawa (Faculty of Science and Technology, Gunma University), Kento Suzuki (Faculty of Science and Technology, Gunma University), Yoshiki Sugawara (Faculty of Science and Tec

キーワード: 自動設計，コンパレータ，部分最適化，木構造探索，遺伝的アルゴリズム＼automatic design，comparator，divided circuit optimization，tree structure search，genetic algorithm

要約(英語): Automatic design of analog integrated circuit is in great demand due to the requirement of the reduction of design time. Optimization algorithms are often used for the automatic design. However, because the optimization algorithm is based on the stochastic method and determines the circuit parameters at random, a lot of circuits which do not operate in principle are generated and simulated to find the optimal circuit. These redundant simulations consume time in vain. In this paper, the automatic design method, which achieves to reduce the redundant simulations, of the topology and element values of the comparator circuit, is proposed. For the decision of the topology, simulation results are utilized to determine the topology, which results in the reduction of numbers of simulations. For the decision of element values, Divided Circuit Optimization which performs optimization for each function block is proposed. The reduction of the optimization target means that HSPICE optimization function ensures to converge. Compared with the conventional method, the proposed method can reduce numbers of simulations to 1/30 and simulation time to 1/3.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.138 No.1 （2018） 特集：電子回路関連技術

本誌掲載ページ: 57-64 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/138/1/138_57/_article/-char/ja/