Register-Transfer-level CPU Simulator for Computer Architecture Education and Its Quantitative Evaluation

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2018/09/01

タイトル(英語): Register-Transfer-level CPU Simulator for Computer Architecture Education and Its Quantitative Evaluation

著者名: Shinya Hara (Kagawa University), Yoshiro Imai (Kagawa University)

著者名(英語): Shinya Hara (Kagawa University), Yoshiro Imai (Kagawa University)

キーワード: Visualization of Computer Education，Web-based e-Learning system，JavaScript，Statistical Analysis

要約(英語): This paper reports an educational tool and its evaluation in order for learners to study Computer Architecture, especially in the higher education of Science and Technology field. This tool, which is called Visual CPU Simulator, can provide graphical simulation of assembly program code (instead of machine language) and demonstration of Register-transfer-level micro-operations inside of CPU, namely precise detail of structure and behavior of inner CPU. This educational tool for CPU simulation has been designed and implemented in Javascript language as Web service. Its users select simulation modes by micro step, by machine cycle and by automatic repetition of such cycles. So they can learn how a computer works graphically, recognize inner structure of CPU easily and understand micro-operation based behavior of CPU effectively. This Simulator has been also evaluated through some kinds of questionnaires by learners in many classroom lectures. It is significantly confirmed that the simulator has been very useful and effective to learn Computer Architecture and organization/performance of CPU through its simulating facilities.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.138 No.9 （2018） 特集Ⅰ：知能メカトロニクス分野と連携する知覚情報技術 特集Ⅱ：国際会議ICESS 2017

本誌掲載ページ: 1123-1130 p

原稿種別: 論文／英語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/138/9/138_1123/_article/-char/ja/