商品情報にスキップ
1 1

LegUpとoLLVMによる難読化制御論理回路の実装

LegUpとoLLVMによる難読化制御論理回路の実装

通常価格 ¥770 JPY
通常価格 セール価格 ¥770 JPY
セール 売り切れ
税込

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2019/09/01

タイトル(英語): Implementation of Obfuscated Control Logic Circuit with LegUp and oLLVM

著者名: 山田 翔太郎(豊橋技術科学大学大学院 電気・電子情報工学課程),市川 周一(豊橋技術科学大学 電気・電子情報工学系),藤枝 直輝(豊橋技術科学大学 電気・電子情報工学系)

著者名(英語): Shotaro Yamada (Electrical and Electronic Information Engineering Course, Toyohashi University of Technology), Shuichi Ichikawa (Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology), Naoki Fujieda (Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology)

キーワード: 知的財産,耐タンパ性,高位合成,LLVM,FPGA  Intellectual property,Tamper resistance,High-level synthesis (HLS),LLVM,FPGA

要約(英語): It is an important issue to protect the intellectual property of software. The authors proposed to conceal some part of software by implementing it as logic circuit. Though the security is further improved by obfuscating the logic circuit, it requires much effort to develop the dedicated obfuscation tool. Matsuoka et al. proposed using the software obfuscation tool, Obfuscator-LLVM (oLLVM), with C-backend (CBE) and Xilinx Vivado HLS (high-level synthesis) to generate the obfuscated logic circuit. This study proposes adopting another HLS, LegUp, to obfuscate logic circuit. The feasibility of these two methods are examined with 12 applications of CHStone benchmark, each of which were evaluated with four obfuscation methods (total 48 cases). In our experiments, Matsuoka's method failed to generate the correct hardware in 5 cases out of 48 cases. Meanwhile, the proposed method successfully generated the correct hardware for all 48 cases. The average latency derived by the proposed method was 43% larger than that by Matsuoka's method. The logic scale derived by the proposed method was also 42% larger (LUT) and 112% larger (FF) than that by Matsuoka's method.

本誌: 電気学会論文誌C(電子・情報・システム部門誌) Vol.139 No.9 (2019) 特集:知能メカトロニクス分野と連携する知覚情報技術

本誌掲載ページ: 952-957 p

原稿種別: 論文/日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/139/9/139_952/_article/-char/ja/

販売タイプ
書籍サイズ
ページ数
詳細を表示する