整数容量比を用いたC-2C D/A変換器の設計手法

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2020/02/01

タイトル(英語): Design Method of C-2C D/A Converter Using Integer Capacitance Ratio

著者名: 関根　慧（東京理科大学理工学研究科電気工学専攻），松浦　達治（東京理科大学理工学部電気電子情報工学科），岸田　亮（東京理科大学理工学部電気電子情報工学科），兵庫　明（東京理科大学理工学部電気電子情報工学科）

著者名(英語): Satoshi Sekine (Department of Electrical Engineering, Graduate School of Science and Technology, Tokyo University of Science), Tatsuji Matsuura (Department of Electrical Engineering, Faculty of Science and Technology, Tokyo University of Science), Ryo Kishida (Department of Electrical Engineering, Faculty of Science and Technology, Tokyo University of Science), Akira Hyogo (Department of Electrical Engineering, Faculty of Science and Technology, Tokyo University of Science)

キーワード: 容量型D/A変換器，C-2C DAC，非2進DAC，寄生容量，容量ミスマッチ，非接地点　　Capacitive D/A Converter (CDAC)，C-2C DAC ，Non-binary DAC，Parasitic capacitance，Capacitor mismatch，Floating node

要約(英語): C-2C D/A converters (DAC) can be designed with fewer unit capacitors than binary weighted capacitive DAC (CDAC), which are advantages in power consumption, operating speed, and circuit area. However, in applications with medium or higher resolution, it needs larger circuit area because an accurate non-integer capacitance ratio is required in order to compensate the influence of the parasitic capacitance at the floating node. In this paper, by configuring C-2C DAC with only a simple integer capacitance ratio, the proposed circuit can be achieved with a smaller circuit area than split CDAC in 9-bit or higher. It also can compensate the variation of parasitic capacitance at floating node by applying the conventional digital correction technique.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.140 No.2 （2020）　特集：エネルギーデータを対象としたIoT，AI活用技術

本誌掲載ページ: 194-203 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/140/2/140_194/_article/-char/ja/