商品情報にスキップ
1 1

高信頼性, 広SOA 100 V N-LDMOSトランジスタの最適化

高信頼性, 広SOA 100 V N-LDMOSトランジスタの最適化

通常価格 ¥770 JPY
通常価格 セール価格 ¥770 JPY
セール 売り切れ
税込

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2020/11/01

タイトル(英語): Optimization of High Reliability and Wide SOA 100 V N-LDMOS Transistor

著者名: 松田 順一(群馬大学),桑名 杏奈(群馬大学),小林 春夫(群馬大学)

著者名(英語): Jun-ichi Matsuda (Gunma University), Anna Kuwana (Gunma University), Haruo Kobayashi (Gunma University)

キーワード: 横型二重拡散MOSFET,信頼性,ホットキャリア,安全動作領域,リサーフ  LDMOS,reliability,hot carrier,SOA,RESURF

要約(英語): This paper describes optimization of a proposed high reliability and wide SOA 100 V N-LDMOS transistor for automotive applications. The drift region of the device is enclosed with two P-type buried layers, dual RESURF structure, and the field plate forming a two-step structure is grounded. The drift region and the field plate were optimized to obtain high hot carrier endurance, high suppression of drain current expansion CE, high breakdown voltage BVDS, and low specific on-resistance RON,SP taking mass production into account. Within the mass production tolerance, the electric field near the gate-side drift region edge of the proposed device is about 70% of that of a conventional device under a high hot carrier generation condition, the drain voltage causing CE of the proposed device is about 20 V higher than that of the conventional device under a high CE generation condition, and the BVDS - RON,SP characteristic of the proposed device is at a state-of-the-art level: BVDS = 131 V and RON,SP = 150 mΩmm2 at the worst case. Furthermore, due to slight changing the tolerance range, high ESD endurance of the proposed device could be obtained at the expense of RON,SP and suppression of CE a little bit.

本誌: 電気学会論文誌C(電子・情報・システム部門誌) Vol.140 No.11 (2020) 特集:電気関係学会関西連合大会

本誌掲載ページ: 1220-1229 p

原稿種別: 論文/日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/140/11/140_1220/_article/-char/ja/

販売タイプ
書籍サイズ
ページ数
詳細を表示する