Multiplied ΔΣ Time to Digital ConverterのNoise shaping改善の検討
Multiplied ΔΣ Time to Digital ConverterのNoise shaping改善の検討
カテゴリ: 論文誌(論文単位)
グループ名: 【C】電子・情報・システム部門
発行日: 2021/01/01
タイトル(英語): A Study on Improvement of Noise Shaping Characteristics of Multiplied ΔΣ Time to Digital Converter
著者名: 嘉藤 貴博(法政大学),安田 彰(法政大学)
著者名(英語): Takahiro Kato (Hosei University), Akira Yasuda (Hosei University)
キーワード: TDC,PLL,ΔΣ,DEM,ループ帯域,ジッタ TDC,PLL,ΔΣ,DEM,loop band width,jitter
要約(英語): Previously, the method has been proposed to reduce the quantization noise of the fractional N-PLL and the spurious due to the reference leak by placing a DLL before the PLL. We have previously proposed Multiplied ΔΣTDC, which solves the phase noise problem and spurious due to DLL delay device manufacturing variation. However, in the previous proposal, there was a trade-off between spurious reduction and quantization noise improvement by ΔΣTDC. In this paper, we propose a Multiplied ΔΣTDC that solves this problem and always has the effect of Noise shaping by ΔΣTDC.
本誌: 電気学会論文誌C(電子・情報・システム部門誌) Vol.141 No.1 (2021) 特集:電子回路関連技術
本誌掲載ページ: 37-43 p
原稿種別: 論文/日本語
電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/141/1/141_37/_article/-char/ja/
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