A 2.8V Input Amplitude CMOS SAR ADC with 0.7V Supply Voltage

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2024/08/01

タイトル(英語): A 2.8V Input Amplitude CMOS SAR ADC with 0.7V Supply Voltage

著者名: Yuanchi Chen (Tokyo City University), Hao San (Tokyo City University)

著者名(英語): Yuanchi Chen (Tokyo City University), Hao San (Tokyo City University)

キーワード: SAR ADC，S/H circuit，amplitude attenuation，bootstrapped switch

要約(英語): This paper presents a 0.7V 12-bit 1.5MS/s SAR ADC incorporates an input amplitude attenuation architecture. To sample large amplitude input signals that exceed the supply voltage (Vin>VDD), a modified bootstrapped switch architecture is proposed, which enhances the dynamic performance of the analog signal sampling switch. The proposed bootstrapped switch is utilized to construct a novel sample-and-hold (S/H) circuit that serves as the front-end for ADCs operating at low supply voltages while tolerating large amplitude input signals. The SAR ADC, which includes this novel S/H circuit, is in 65nm SOTB CMOS technology. It achieves a simulated SNDR of 65.71dB, a SFDR of 81.33dB and an ENOB of 10.62 bits with a full-scale input amplitude of Vin_pp=2.8V (peak-to-peak voltage) at 0.7V supply voltage VDD.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.144 No.8 （2024） 特集Ⅰ：Smart Cityを支える高度な無線通信，センシング及び情報処理　特集Ⅱ：人と人とを繋ぐ情報・システム技術

本誌掲載ページ: 771-776 p

原稿種別: 論文／英語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/144/8/144_771/_article/-char/ja/