Identification Method of Parasitic Inductances in a Power Electronics Circuit Board using TDR

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2011/08/01

タイトル(英語): Identification Method of Parasitic Inductances in a Power Electronics Circuit Board using TDR

著者名: Satoshi Hashino (Tokyo Metropolitan University), Toshihisa Shimizu (Tokyo Metropolitan University)

著者名(英語): Satoshi Hashino (Tokyo Metropolitan University), Toshihisa Shimizu (Tokyo Metropolitan University)

キーワード: high power density converter，extraction method of parasitic inductances，time domain reflectometry

要約(英語): Accurate identification of parasitic parameters on a printed circuit board (PCB) and establishment of an effective design method by considering the parasitic components in a power electronics circuit will become major technological issues to increase the power density of power converters. This study focuses on time domain reflectometry (TDR) method in order to identify and to measure the value of parasitic elements on the PCB in which circuit components are closely mounted. A printed circuit board for high power density converter can be effectively designed by using measured value of parasitic parameters. In this paper, two-step measuring method of measuring multiple parasitic inductances of those existing on a buck chopper PCB is proposed. In this method, a discrimination of the location of parasitic elements is identified on the first step, and the values of each parasitic component are measured on the second step. The accuracy of the measured parasitic inductances is verified through the comparison of experimental and simulation results.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.131 No.8 （2011） 特集：IPEC-Sapporo 2010

本誌掲載ページ: 1036-1041 p

原稿種別: 論文／英語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/131/8/131_8_1036/_article/-char/ja/