半導体歩留り解析のための回帰木に基づく仮説検証手法の提案

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2011/10/01

タイトル(英語): A Hypothesis Verification Method Using Regression Tree for Semiconductor Yield Analysis

著者名: 津田　英隆（富士通（株）），白井　英大（富士通セミコンダクターITシステムズ（株）），寺邊　正大（（株）三菱総合研究所），橋本　和夫（東北大学大学院情報科学研究科），篠原　歩（東北大学大学院情報科学研究科）

著者名(英語): Hidetaka Tsuda (Fujitsu Limited), Hidehiro Shirai (Fujitsu Semiconductor IT Systems Limited), Masahiro Terabe (Mitsubishi Research Institute, Inc.), Kazuo Hashimoto (Graduate School of Information Sciences, Tohoku University), Ayumi Shinohara (Graduate School of Information Sciences, Tohoku University)

キーワード: 半導体，歩留り解析，回帰木分析，属性，仮説検証，不良要因特定　　semiconductor，yield analysis，regression tree analysis，attribute，hypothesis verification，failure cause identification

要約(英語): Several researchers have reported the regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying the regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the route node do not indicate the hypothesized causes of failure. We propose a method for verifying the hypothesized causes of failure, which reduces the number of verification hypotheses. Our method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying the regression tree analysis separately to each set of analysis data, and merging and sorting attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of the regression tree analysis for semiconductor yield.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.131 No.10 （2011）

本誌掲載ページ: 1232-1239 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/131/10/131_10_1232/_article/-char/ja/