零相電圧を利用した漏えい電流低減法の提案と検証

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2012/12/01

タイトル(英語): Proposal and Verification of a Technique for Reducing Leakage Current Using Zero-Sequence Voltage

著者名: 綾野　秀樹（東京工業高等専門学校），佐藤　優貴（東京工業高等専門学校），松井　義弘（東京工業高等専門学校）

著者名(英語): Hideki Ayano (Tokyo National College of Technology), Yuki Sato (Tokyo National College of Technology), Yoshihiro Matsui (Tokyo National College of Technology)

キーワード: 漏えい電流，零相電圧，コモンモード，コモンモードチョーク，EMI　　leakage current，zero-sequence voltage，common-mode，common-mode choke，EMI

要約(英語): This paper proposes a technique for reducing the leakage current that flows into a power source as conductive noise. Output voltages of an inverter system consist of a d-axis voltage that generates a flux current, a q-axis voltage that generates a torque current, and a zero-sequence voltage. The zero-sequence voltage does not affect the driving characteristics of the load. The proposed method applies a zero-sequence voltage to the output voltage references in a circuit containing grounding capacitors. As a result, the fundamental frequency component of the zero-sequence voltage produced by the inverter decreases and the leakage current reduces. This allows a decrease in the size of the common-mode chokes. The leakage current can be reduced further by increasing the additional zero-sequence voltage reference. The experimental results show that the proposed method can reduce the leakage current when the zero-sequence voltage is applied.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.132 No.12 （2012）

本誌掲載ページ: 1141-1148 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/132/12/132_1141/_article/-char/ja/