Bilateral Filterのハードウェア化による高速化

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2013/02/01

タイトル(英語): Hardware Acceleration of Bilateral Filters

著者名: 伊佐　周平（千葉大学工学部メディカルシステム工学科），山田　親稔（沖縄工業高等専門学校情報通信システム工学科），長田　康敬（琉球大学工学部電気電子工学科）

著者名(英語): Shuhei Isa (Department of Medical System Engineering, Faculty of Engineering,Chiba University), Chikatoshi Yamada (Department of Information and Communication System Engineering,Okinawa National College of Technology), Yasunori Nagata (Department of Electrical and Electronics Engineering,University of the Ryukyus)

キーワード: FPGA，画像処理，Bilateral Filter，リアルタイム処理　　FPGA，image processing，bilateral filter，real-time processing

要約(英語): A bilateral filter (BF) is a nonlinear filter that performs edge-preserving smoothing. In recent years, BF has been used in a wide variety of fields such as computer vision and computer graphics, and its applications include medical image processing. However, as compared to other filters, BF has large computational and time requirements. BF can be effectively used as a pre-processing step to speed up processing. In this paper, we consider a BF implemented at a one-chip circuit scale on a field-programmable gate array (FPGA). Furthermore, we aim to speed up floating-point pipelined arithmetic operations and processing by adopting a multiplication-based divider. The results show that hardware processing is approximately 20.93 times faster than software processing. Therefore, high-speed applications using BF are possible without the need for large equipment such as workstations or GPUs. Finally, it is suggested that real-time processing is feasible if a BF is applied as a pre-processing step.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.133 No.2 （2013） 特集：Okinawa型ロボット・組み込みシステム

本誌掲載ページ: 132-138 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/133/2/133_132/_article/-char/ja/