大型半導体パッケージを用いたインバータの低インダクタンス実装技術の開発

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2014/04/01

タイトル(英語): Low-Inductance Mounting Technique for Inverter with Large Semiconductor Packages

著者名: 越智　健太郎（(株) 日立製作所），三島　彰（(株) 日立製作所），畑中　歩（(株) 日立製作所），金澤　拓朗（(株) 日立製作所）

著者名(英語): Kentaro Ochi (Hitachi, Ltd.), Akira Mishima (Hitachi, Ltd.), Ayumu Hatanaka (Hitachi, Ltd.), Takuro Kanazawa (Hitachi, Ltd.)

キーワード: 転流経路インダクタンス，樹脂パッケージ，磁界解析，ラミネート構造，渦電流シールド　　commutation inductance，resin package，magnetic field analysis，laminate structure，eddy current shield

要約(英語): This paper proposes a low-inductance mounting technique for an inverter with large semiconductor packages. The following two measures are adopted to decrease the circuit inductance. One is the use of the low-inductance ground pattern of a printed wiring board. The ground pattern is connected in parallel to the main bus bar with lower resistance and higher inductance. The surge current with high di/dt flows selectively in the lower-inductance ground pattern, and the continuous normal current flows in the lower-resistance main bus bar. The other measure is the utilization of an eddy current induced in the heat sink. The eddy current, decreasing circuit inductance, increases in inverse proportion to the distance between the heat sink and a conductor connecting two semiconductor packages. Because of these measures, the circuit inductance decreases to 38% of that of a conventional circuit.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.134 No.4 （2014）

本誌掲載ページ: 392-397 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/134/4/134_392/_article/-char/ja/