サージ電圧抑制とスイッチング損失の低減を目的とした相互誘導を利用したゲート駆動回路実装

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2018/02/01

タイトル(英語): Implementation of Gate Driver Circuit for Suppressing Both Surge Voltage and Switching Loss by Using Mutual Inductance

著者名: 緒形　航（首都大学東京），和田　圭二（首都大学東京）

著者名(英語): Ko Ogata (Tokyo Metropolitan University), Keiji Wada (Tokyo Metropolitan University)

キーワード: SiC-MOSFET，寄生パラメータ，相互インダクタンス，スイッチング試験　　SiC-MOSFET，parasitic parameters，mutual inductance，switching experiment

要約(英語): Recently, the development of power devices, such as SiC and GaN devices has lead to the increase in research on the influence of parasitic parameters, such as wiring inductance, parasitic capacitance, and packaging inductance in power converter circuits. In general, the converter circuit has several circuit loops, including higher-voltage circuit, gate-drive, and low voltage control circuits, on one printed circuit board. However, studies have discussed the influence of a mutual inductance between higher-voltage and gate-drive circuits. Mutual inductances between the circuits could influence the switching characteristics, such as surge voltage and switching loss. This paper describes an influence of mutual inductance on the higher-voltage and gate-drive circuits, and presents the simulation and experimental results rated at 500V and 20A using SiC-MOSFET and SBD. Moreover, this paper proposes an implementation of a gate drive circuit by using mutual inductance for suppression of both surge voltage and switching loss.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.138 No.2 （2018） 特集：J-RAIL 2016

本誌掲載ページ: 135-140 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/138/2/138_135/_article/-char/ja/