低インダクタンスを実現する厚銅多層基板を用いたSiC-MOSFETインバータの主回路設計

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2020/02/01

タイトル(英語): Design of Main Circuit for an SiC-MOSFET Inverter Using a Thick Copper Multilayer PCB to Minimize Stray Inductance

著者名: 石川　光亮（北海道大学大学院情報科学研究科），小笠原　悟司（北海道大学大学院情報科学研究科），竹本　真紹（北海道大学大学院情報科学研究科），折川　幸司（北海道大学大学院情報科学研究科）

著者名(英語): Kohsuke Ishikawa (Graduate School of Information Science and Technology, Hokkaido University), Satoshi Ogasawara (Graduate School of Information Science and Technology, Hokkaido University), Masatsugu Takemoto (Graduate School of Information Science and Technology, Hokkaido University), Koji Orikawa (Graduate School of Information Science and Technology, Hokkaido University)

キーワード: SiC-MOSFET，厚銅多層基板，配線インダクタンス，PCB設計　　SiC-MOSFET，thick copper multilayer PCB，stray inductance，PCB design

要約(英語): Inverters using SiC or GaN power devices can achieve high frequency and high efficiency operation. To achieve high efficiency, the switching characteristics of these power devices are important because stray inductances in the main circuit of the inverter have a strong influence on the switching characteristics. To reduce switching loss and surge voltage, minimization of stray inductance in the main circuit is required for a high-frequency PWM inverter. This paper describes design guidelines for high-frequency inverters that achieve low inductance. The PCB design guideline on a thick multilayer PCB is derived from the inductance calculation using 3D-FEA. It is shown experimentally that the stray inductance of the designed PCB can be reduced to the same level as the inductance inside the power devices. Experimental results verify that a prototype can achieve high-speed switching and suppress a surge voltage. A load test is demonstrated to evaluate the main circuit efficiency in a half-bridge inverter at 100kHz.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.140 No.2 （2020）

本誌掲載ページ: 89-98 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/140/2/140_89/_article/-char/ja/