Chip Layout Optimization of SiC Power Modules Based on Multiobjective Electro-Thermal Design Strategy

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門（英文）

発行日: 2022/01/01

タイトル(英語): Chip Layout Optimization of SiC Power Modules Based on Multiobjective Electro-Thermal Design Strategy

著者名: Shuhei Fukunaga (Division of Electrical, Electronic and Infocommunications Engineering, Graduate School of Engineering, Osaka University), Tsuyoshi Funaki (Division of Electrical, Electronic and Infocommunications Engineering, Graduate School of Engineeri

著者名(英語): Shuhei Fukunaga (Division of Electrical, Electronic and Infocommunications Engineering, Graduate School of Engineering, Osaka University), Tsuyoshi Funaki (Division of Electrical, Electronic and Infocommunications Engineering, Graduate School of Engineering, Osaka University)

キーワード: power electronics，layout，optimization method，design automation，power module，finite element method

要約(英語): Electro-thermal co-design of power modules is required to maximize the capabilities of promising power semiconductor devices. The chip layout on the substrate, which is restricted by the size of the power module substrate, determines the electrical and thermal characteristics of the power module. This paper proposes a chip layout optimization strategy for power modules based on a multiobjective electro-thermal design algorithm. The parasitic inductance and thermal resistance of the SiC power module are evaluated using the unified simulation model based on the multiphysics solver of the finite element method. The proposed multiobjective optimal design approach uses non-dominated sorting genetic algorithm II (NSGA-II) and the developed simulation model to obtain a Pareto front for the parasitic inductance and thermal resistance of the power module. Module samples with the obtained Pareto front parameters are experimentally characterized and validated with numerical simulation results.

本誌: IEEJ Journal of Industry Applications Vol.11 No.1 （2022）

本誌掲載ページ: 157-162 p

原稿種別: 論文／英語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejjia/11/1/11_21006215/_article/-char/ja/