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Gate Drive Circuit Implementation for Parallel Connection of Power Devices Considering Parasitic Inductance

Gate Drive Circuit Implementation for Parallel Connection of Power Devices Considering Parasitic Inductance

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カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門(英文)

発行日: 2023/03/01

タイトル(英語): Gate Drive Circuit Implementation for Parallel Connection of Power Devices Considering Parasitic Inductance

著者名: Yudai Funaki (Tokyo Metropolitan University), Keiji Wada (Tokyo Metropolitan University)

著者名(英語): Yudai Funaki (Tokyo Metropolitan University), Keiji Wada (Tokyo Metropolitan University)

キーワード: current balance,gate drive circuit,parallel connection,parasitic inductance

要約(英語): SiC devices are potential future power devices because of their higher switching speed and lower ON resistance than those of Si devices. Research and development efforts to apply them in medium- and large-capacity power conversion circuits are underway. However, SiC power devices in TO packages, which are general-purpose packages, are difficult to apply in high-current applications owing to their low current ratings. Therefore, increasing the capacity of power devices by connecting them in parallel is being studied. However, the current imbalance during switching due to the differences in device characteristics and variations in parasitic inductance is problem. This study proposed a current-balancing procedure focused on the parasitic inductances around power devices and gate drive circuit implementation. The proposed method was verified by conducting double-pulse tests at 300V and 200A.

本誌: IEEJ Journal of Industry Applications Vol.12 No.2 (2023) Special Issue on “Motion Control and its Related Technologies”

本誌掲載ページ: 176-182 p

原稿種別: 論文/英語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejjia/12/2/12_22006323/_article/-char/ja/

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