パイプライン化によるブロック構造ニューラルネットワークの高速化

カテゴリ: 研究会(論文単位)

論文No: ST18102

グループ名: 【C】電子・情報・システム部門 システム研究会

発行日: 2018/09/27

タイトル(英語): High performance Block-Based Neural Network Model by pipeline processing

著者名: 李 建道(メンター・グラフィックス・ジャパン／横浜国立大学),濱上 知樹(横浜国立大学)

著者名(英語): Kundo Lee(Mentor Graphics Japan / Yokohama National University),Tomoki Hamagami(Yokohama National University)

キーワード: ＦＰＧＡ|進化型ハードウェア|遺伝的アルゴリズム|パイプライン|ブロック構造ニューラルネットワーク|FPGA|Evolvable Hardware|Genetic Algorithm|Pipeline|Block-Based Neural Network

要約(日本語): The structure and weight in Block-Based Neural Network (BBNN) are optimized by utilizing genetic algorithm. The architecture of BBNN consists of a two-dimensional (2-D) array of basic block with four input/output nodes and connection weights for block’s output. To propose easier hardware implementation like Field Programmable Gate Array (FPGA), integer weights are used in the basic block. Each block in BBNN can be one of the four different basic types. However, BBNN’s structural change needs hardware reconfiguration and the cost is very high. To reduce the reconfiguration cost, Smart Block-based Neuron (SBbN) has been proposed. SBbN preserves all weights even unnecessary for some types, and thus it consumes redundant hardware resource. A new model of BBNNs has been proposed and it eliminates the resource redundancy of SBbN. However, new approach does not provide parallel com- putation in left and rightward signal flow. This paper presents a pipeline architecture with a parallel computation in a horizontal fashion.

要約(英語): The structure and weight in Block-Based Neural Network (BBNN) are optimized by utilizing genetic algorithm. The architecture of BBNN consists of a two-dimensional (2-D) array of basic block with four input/output nodes and connection weights for block’s output. To propose easier hardware implementation like Field Programmable Gate Array (FPGA), integer weights are used in the basic block. Each block in BBNN can be one of the four different basic types. However, BBNN’s structural change needs hardware reconfiguration and the cost is very high. To reduce the reconfiguration cost, Smart Block-based Neuron (SBbN) has been proposed. SBbN preserves all weights even unnecessary for some types, and thus it consumes redundant hardware resource. A new model of BBNNs has been proposed and it eliminates the resource redundancy of SBbN. However, new approach does not provide parallel com- putation in left and rightward signal flow. This paper presents a pipeline architecture with a parallel computation in a horizontal fashion.

原稿種別: 日本語

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