データの冗長性に着目したキャッシュの回路面積削減

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2013/08/01

タイトル(英語): Reducing Cache Hardware by Focusing on Data Redundancy

著者名: 小林　良太郎（豊橋技術科学大学），松川　大佑（豊橋技術科学大学），下村　佳生（豊橋技術科学大学），落合　裕也（豊橋技術科学大学），嶋田　創（奈良先端科学技術大学院大学）

著者名(英語): Ryotaro Kobayashi (Toyohashi University of Technology), Daisuke Matsukawa (Toyohashi University of Technology), Yoshio Shimomura (Toyohashi University of Technology), Hiroya Ochiai (Toyohashi University of Technology), Hajime Shimada (Nara Institute of Science and Technology)

キーワード: プロセッサ，キャッシュ，回路面積削減，ビット分割　　proecssor，cache，reducing circuit area，bit division

要約(英語): There's one reason to utilize cache that mitigates processor performance limitation comes from data transfer bandwidth. Recently, cache size expansion is required in this use because data transfer bandwidth requirement is increasing for recent large data size and multi-core trends. However, cache size expansion is unwelcome because it causes problems come from circuit area and power consumption viewpoint. This paper focuses a data redundancy with the goal of reducing cache size and proposes a mechanism that does not store redundant data into cache. The proposed mechanism divides data into Higher Bit and Lower Bit, that stored into Higher Cache and Lower Cache, respectively. We reduced Higher Cache size to half size by keeping 46% redundant data in Higher Bit area not to store into Higher Cache. The evaluation results show that the proposed mechanism increases IPC by 3.3% on average compared with same circuit area conventional cache under SPECCPU2000 benchmarks.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.133 No.8 （2013） 特集：パワー半導体光源とその応用技術

本誌掲載ページ: 1597-1606 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/133/8/133_1597/_article/-char/ja/