ハードウェア割り込み優先度を利用した割り込み処理の優先度継承セマフォの実現方式

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2013/11/01

タイトル(英語): A Priority Inherit Semaphore Mechanism of Interrupt Service Routine Using Hardware Interrupt Level

著者名: 南角　茂樹（大阪電気通信大学大学院），川上　博行（ウインドリバー（株）），小泉　寿男（東京電機大学），福田　晃（九州大学大学院システム情報科学研究院）

著者名(英語): Shigeki Nankaku (Osaka Electro-Communication University), Hiroyuki Kawakami (Wind River KK.), Hisao Koizumi (Tokyo Denki University), Akira Fukuda (Faculty of Information Science and Electrical Engineering, Kyushu University)

キーワード: 組込みシステム，組込み，ISR，優先度，優先度逆転，優先度継承　　Embedded Systems，Embedded，Interrupt Service Routine，Priority，Priority Inversion，Priority Inherit

要約(英語): For embedded systems, concurrency is required to respond to various changes in real world. Real-time processing is required also, because the response typically has a time limit. The concurrency is implemented by processing Tasks or Interrupt Service Routines (ISRs) concurrently. And the necessity of mutual exclusion arises in concurrent processing, to maintain integrity of shared data. Task execution is scheduled by Real-time OS (RTOS), and mutual exclusion is serviced by semaphore. However approximately 30% of embedded systems do not use RTOS. These systems have no notion of Tasks, and are purely driven by ISRs. As the sole mutual exclusion method between ISRs, a pair of interrupt disable/enable instructions provided by CPU is used in these systems. This method enables a lower priority ISR to protect its critical section from higher priority ISRs, but it also defers execution of unrelated ISRs as it disables all external interrupts. We have resolved this timing issue with an ISR-callable semaphore, but that design was not priority inversion safe. Namely a middle priority ISR may indirectly block a higher priority ISR if this higher priority ISR waits for a semaphore from a lower priority ISR, because the lower priority ISR can be preempted by the middle priority ISR. Priority inheritance is an effective protection method against this priority inversion problem, and it is expected to improve real-time performance of OS-less embedded systems. This paper proposes an ISR-callable priority inheritance semaphore which protects ISRs from priority inversion using hardware interrupt mechanism.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.133 No.11 （2013） 特集：電気関係学会関西連合大会

本誌掲載ページ: 2053-2061 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/133/11/133_2053/_article/-char/ja/