検算対策回路の特性を利用した電力解析攻撃とその評価

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2016/12/01

タイトル(英語): Countermeasure Aware Power Analysis Attack and its Evaluation

著者名: 池崎　良哉（名城大学大学院理工学研究科），野崎　佑典（名城大学大学院理工学研究科），吉川　雅弥（名城大学理工学部）

著者名(英語): Yoshiya Ikezaki (Dept. of Information Engineering Graduate School of Meijo University), Yusuke Nozaki (Dept. of Information Engineering Graduate School of Meijo University), Masaya Yoshikawa (Dept. of Information Engineering Meijo University)

キーワード: 電力解析，AES，検算対策回路，セキュリティ，耐タンパ性，サイドチャネル攻撃　　Power Analysis，AES，Back-check Circuit，Security，Tamper Resistance，Side-channel Attack

要約(英語): Smart cards, such as credit cards and cash cards, protect confidential information using cryptographic circuits. Since cryptographic circuits protect confidential information, various attacks often target cryptographic circuits. To attack cryptographic circuits, a method called side-channel attacks has been reported. Side-channel attacks reveal cipher keys by intentionally mixing faults in a cryptographic circuit or by measuring the power consumption of a cryptographic circuit during its operation. A method using a back-check system was reported as a typical countermeasure of the advanced encryption standard (AES) against a fault analysis attack which uses a cryptogram with faults and a correct cryptogram. This study proposes a new power analysis method against a countermeasure with the back-check system. The proposed method utilizes the circuit structure of back-check system for the analysis. To our knowledge, this is the first power analysis attack against countermeasure of fault analysis attack. Experiments using a LSI prove the validity of the proposed method.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.136 No.12 （2016） 特集Ⅰ：電気・電子・情報関係学会東海支部連合大会　特集Ⅱ：国際会議ACIS 2014/2015

本誌掲載ページ: 1621-1628 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/136/12/136_1621/_article/-char/ja/