多相クロック分周器に基づく一定パルス間隔の周波数逓倍型ディジタル位相同期ループ

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2018/04/01

タイトル(英語): Multiple Frequency Digital Phase-Locked Loop Based on Multi-Phase Clock Divider with Constant Pulse Interval

著者名: 矢原　充敏（東海大学福岡短期大学），藤本　邦昭（東海大学基盤工学部電気電子情報工学科），清田　英夫（東海大学基盤工学部電気電子情報工学科）

著者名(英語): Mitsutoshi Yahara (Tokai University Fukuoka Junior College), Kuniaki Fujimoto (School of Industrial and Welfare Engineering, Tokai University), Hideo Kiyota (School of Industrial and Welfare Engineering, Tokai University)

キーワード: PLL，逓倍，一定パルス間隔，多相クロック　　PLL，multiple frequency，constant pulse interval，multi-phase clock

要約(英語): In the mobile communication equipment, the clock generator for driving each system is required to have a fast pull-in time, multiple signal of constant pulse interval, synchronization range, low output jitter, and wide lock-in range characteristics.In this paper, multiple frequency MC-DCPLL is proposed. In this loop, the pulse width error of the multiplied output signal is a time within one phase difference of the multi-phase clock regardless of the multiplication ratio. The output jitter in the steady state is always within one phase difference of the multi-phase clock. Since it is a control method by dividing ratio changeable type, the lock-in range is extremely wide. Also, the initial pull-in time is always completed in one cycle of the input signal without being influenced by the multiplication ratio. It is clarified by theory and simulation that these characteristics can be obtained.From the above, the versatility of the proposed multiple frequency MC-DCPLL is extremely high, and it can be expected to be used for clock sources etc. in various mobile communication equipment systems.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.138 No.4 （2018） 特集：信号処理と制御の融合に基づく新領域の創出

本誌掲載ページ: 387-394 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/138/4/138_387/_article/-char/ja/