2値化ニューラルネットワークに特化した超小型プロセッサの設計・解析

カテゴリ: 論文誌(論文単位)

グループ名: 【C】電子・情報・システム部門

発行日: 2021/02/01

タイトル(英語): Design and Verification of Ultra-small Processor with Specializes Binarized Neural Network

著者名: 増淵　友一（愛知工業大学），伊藤　裕也（愛知工業大学），津田　紀生（愛知工業大学），五島　敬史郎（愛知工業大学）

著者名(英語): Tomokazu Masubuchi (Aichi Institute of Technology), Yuya Ito (Aichi Institute of Technology), Norio Tsuda (Aichi Institute of Technology), Keishiro Goshima (Aichi Institute of Technology)

キーワード: 中央処理装置，小型プロセッサ，ニューラルネットワーク，集積回路_x000D_　　CPU，micro processor，neural network，integrated circuit

要約(英語): A lot of multiplication circuits and a large-scale memory are required to operate a neural network. However, it is also necessary to use a low-power consumption and small-scale processor with a neural network for an embedded image-processing system. A binarized neural network (BNN) operating on the basis of the binary operation method is one of the candidates for solving such problems because the multiplication circuit is unnecessary, and a relatively small memory is required. In this study, an ultrasmall processor was designed with a specialized BNN based on the processor with a very small area for function, “Pilaf.” The processor designed is called “Pulin,” in which a control circuit is added that can access a large memory area and an image-processing arithmetic circuit. Despite the addition of some circuits, the design of Pulin demonstrates the same chip area as that of Pilaf because the architecture and the state machine are optimized. In addition, the processing time taken in the case of the neural network execution was reduced to approximately half that of the conventional processor. In addition, a large-scale integration (LSI) circuit was fabricated, and the delay time and operation speed of Pulin were analyzed using an LSI tester.

本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.141 No.2 （2021） 特集I：IoT社会の進歩を促進するワイヤレス技術　　特集Ⅱ：ディジタル信号処理のためのシステム技術

本誌掲載ページ: 165-171 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/141/2/141_165/_article/-char/ja/