部分再構成を用いたプロセッサの耐故障化手法に関する検討

カテゴリ: 論文誌(論文単位)

グループ名: 【D】産業応用部門

発行日: 2019/02/01

タイトル(英語): Research on Fault Tolerant Processor using Dynamic Reconfiguration

著者名: 荻堂　盛也（沖縄工業高等専門学校），山田　親稔（沖縄工業高等専門学校），宮城　桂（沖縄工業高等専門学校），市川　周一（豊橋技術科学大学），藤枝　直輝（豊橋技術科学大学）

著者名(英語): Seiya Ogido (National Institute of Technology, Okinawa College), Chikatoshi Yamada (National Institute of Technology, Okinawa College), Kei Miyagi (National Institute of Technology, Okinawa College), Shuichi Ichikawa (Toyohashi University of Technology), Naoki Fujieda (Toyohashi University of Technology)

キーワード: FPGA，動的部分再構成，フォールトトレラント，単一縮退故障　　FPGA，dynamic partial reconfiguration，fault tolerant，single event burnout

要約(英語): In this paper, we propose a reconfigurable fault tolerant architecture that can recover from failure status with spare space. Recently, progress in semiconductor technology has been remarkable due to microfabrication of devices. The semiconductor technique plays an important role in artificial satellites and aircraft. Furthermore, it has guaranteed the reliability of the circuits by the multiplexing structure. However, in embedded systems, space-saving is regarded to be as important as reliability. In the traditional approach, the area overhead tends to become large. Reconfigurable fault tolerance can achieve high area efficiency. In this research, we aim to improve the reliability and area efficiency for a single stuck-at fault of the processor. In this article, we reproduce the proposed method using Tcl script and proposed standalone fault tolerant operation using embedded Linux.

本誌: 電気学会論文誌D（産業応用部門誌） Vol.139 No.2 （2019） 特集：ドローンとロボット組み込み/サスティナブルシステム

本誌掲載ページ: 187-192 p

原稿種別: 論文／日本語

電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejias/139/2/139_187/_article/-char/ja/